MPC5748 CAN FD

shijiaguo — Tue, 31 Jan 2017 19:29:47 GMT

Hello all!

I'm running into a timing issue while configuring the CAN FD on MPC5748G micro.

I’m using 40MHz F40 clock as CAN oscillator clock (fCANCLK). And my arbitration bit rate is set at 500K, and the data bit rate is set to be twice as that =1000K. The PSEG and DIV settings for arbitration and data are as follows:

The arbitration phase turns out to be ok. However, the data rate in the data phase is slightly imperfect. The data is supposed to be 1000ns/bit, however, on my scope it’s showing ~960ns/bit. Here’s the screenshot (yellow and blue are CAN high and low, red is CANH – CANL, I’m sending data 0b1010101….). This is causing the Canalyzer not being able to receive data correctly. Does anyone have any idea what’s happening and how to make the timing more accurate?

Re: MPC5748 CAN FD

PetrS — Wed, 01 Feb 2017 13:29:54 GMT

Hi Shijia,

The length of data bit time is calculated as SYNC + FPROPSEG + (FPSEG1+1) + (FPSEG2+1).

FPROPSEG, FPSEG1, FPSEG2 are values written into FDCBT register.

So for your setting just increase FPROPSEG.

However it is recommended to have the same time quanta length for the data phase and set the sample time somewhere in the middle of the data bit time. So you can recalculate your setting to have the same prescaler for both nominal and data bit time.

BR, Petr

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MPC5748 CAN FD

Re: MPC5748 CAN FD