topic Re: MPC5604 DSPI TX/RX FIFO queue bytes size? in MPC5xxx https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637440#M6180 <HTML><HEAD></HEAD><BODY><P>hi,jive!</P><P> can read PC14 input level when config this pin as SPI1 MISO (my target iic is MPC5604B)?</P></BODY></HTML> Thu, 23 Feb 2017 06:02:22 GMT Zhimin 2017-02-23T06:02:22Z MPC5604 DSPI  TX/RX FIFO queue bytes size? https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637437#M6177 <HTML><HEAD></HEAD><BODY><P><SPAN style="color: #51626f; background-color: #ffffff;">Dear Team:</SPAN></P><P><SPAN style="color: #51626f; background-color: #ffffff;">&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;MPC5604 DSPI &nbsp;TX/RX FIFO&nbsp;queue bytes size?</SPAN></P><P><SPAN style="color: #51626f; background-color: #ffffff;">TKS</SPAN></P><P style="min-height: 8pt; padding: 0px; border: 0px;">&nbsp;</P><P style="border: 0px;">&nbsp;</P><P style="border: 0px;"><SPAN style="border: 0px; font-weight: inherit; font-size: 10pt;">Best Regards,</SPAN></P><P style="border: 0px;"><SPAN style="border: 0px; font-weight: inherit; font-size: 10pt;">Atom</SPAN></P></BODY></HTML> Wed, 15 Feb 2017 09:05:37 GMT https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637437#M6177 Zhimin 2017-02-15T09:05:37Z Re: MPC5604 DSPI TX/RX FIFO queue bytes size? https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637438#M6178 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P></P><P>Which device did you mean?</P><P><SPAN style="font-size: 11.0pt;">There is 4-deep TX/RX FIFO on the MPC5604B and 5-deep TX/RX FIFO on the MPC5604P, MPC5604E.</SPAN></P><P></P><P><SPAN style="font-size: 11.0pt;">BR, Petr</SPAN></P></BODY></HTML> Wed, 15 Feb 2017 09:26:31 GMT https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637438#M6178 PetrS 2017-02-15T09:26:31Z Re: MPC5604 DSPI TX/RX FIFO queue bytes size? https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637439#M6179 <HTML><HEAD></HEAD><BODY><P>MPC5604B</P></BODY></HTML> Wed, 15 Feb 2017 09:29:47 GMT https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637439#M6179 Zhimin 2017-02-15T09:29:47Z Re: MPC5604 DSPI TX/RX FIFO queue bytes size? https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637440#M6180 <HTML><HEAD></HEAD><BODY><P>hi,jive!</P><P> can read PC14 input level when config this pin as SPI1 MISO (my target iic is MPC5604B)?</P></BODY></HTML> Thu, 23 Feb 2017 06:02:22 GMT https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637440#M6180 Zhimin 2017-02-23T06:02:22Z Re: MPC5604 DSPI  TX/RX FIFO queue bytes size? https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637441#M6181 <HTML><HEAD></HEAD><BODY><P>the PC14 cannot be set as SPI1 MISO, did you mean PC4?</P><P>For the PC4 if SIU.PCR[36]. IBE bit is set you can read the input level from SIU.GPDI[36] register too.</P><P></P><P>BR, Petr</P></BODY></HTML> Fri, 24 Feb 2017 09:50:51 GMT https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637441#M6181 PetrS 2017-02-24T09:50:51Z Re: MPC5604 DSPI  TX/RX FIFO queue bytes size? https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637442#M6182 <HTML><HEAD></HEAD><BODY><P>TKS!</P></BODY></HTML> Sun, 26 Feb 2017 09:57:37 GMT https://community.nxp.com/t5/MPC5xxx/MPC5604-DSPI-TX-RX-FIFO-queue-bytes-size/m-p/637442#M6182 Zhimin 2017-02-26T09:57:37Z