https://community.nxp.com/t5/MPC5xxx/MPC5674F-Pipelined-SSRAM/m-p/635427#M6083 <HTML><HEAD></HEAD><BODY><P>Hello NXP:<BR />I use MPC5674F&nbsp;&nbsp;EBI, the burst mode on CS0. Can the Pipelined SRAM (with NoBL) be used?&nbsp; The SSRAM&nbsp; is CY7C1370KVE33.</P></BODY></HTML> Wed, 08 Mar 2017 14:59:49 GMT ypchen 2017-03-08T14:59:49Z https://community.nxp.com/t5/MPC5xxx/MPC5674F-Pipelined-SSRAM/m-p/635427#M6083 <HTML><HEAD></HEAD><BODY><P>Hello NXP:<BR />I use MPC5674F&nbsp;&nbsp;EBI, the burst mode on CS0. Can the Pipelined SRAM (with NoBL) be used?&nbsp; The SSRAM&nbsp; is CY7C1370KVE33.</P></BODY></HTML> Wed, 08 Mar 2017 14:59:49 GMT https://community.nxp.com/t5/MPC5xxx/MPC5674F-Pipelined-SSRAM/m-p/635427#M6083 ypchen 2017-03-08T14:59:49Z https://community.nxp.com/t5/MPC5xxx/MPC5674F-Pipelined-SSRAM/m-p/635428#M6084 <HTML><HEAD></HEAD><BODY><P>Our reference designs always contain Flow-through memories. However MPC55xx/56xx is capable of interfacing with SRAMs that operate in either Flow Through or Pipeline mode that is usable with the addition of wait states in the MCU’s read timing.</P><P>&nbsp;</P><P>I could recommend you to see following third party document dealing with this topic:</P><P><A href="http://gsitechnology.com/AppNotes/AN1020.pdf">http://gsitechnology.com/AppNotes/AN1020.pdf</A></P></BODY></HTML> Thu, 09 Mar 2017 08:20:50 GMT https://community.nxp.com/t5/MPC5xxx/MPC5674F-Pipelined-SSRAM/m-p/635428#M6084 davidtosenovjan 2017-03-09T08:20:50Z https://community.nxp.com/t5/MPC5xxx/MPC5674F-Pipelined-SSRAM/m-p/635429#M6085 <HTML><HEAD></HEAD><BODY><P>ok , thanks</P></BODY></HTML> Thu, 09 Mar 2017 13:36:42 GMT https://community.nxp.com/t5/MPC5xxx/MPC5674F-Pipelined-SSRAM/m-p/635429#M6085 ypchen 2017-03-09T13:36:42Z