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    <title>MPC5xxx中的主题 MPC5200 SDRAM timing clarification</title>
    <link>https://community.nxp.com/t5/MPC5xxx/MPC5200-SDRAM-timing-clarification/m-p/380084#M486</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;On the MPC5200 SDRAM timing, standard SDRAM, read timing, the data setup is specified as a max of 0.3ns.&amp;nbsp; Normalli I see setup time specified as minimums.&amp;nbsp; Is this an error, or is there any clarification of why this is specified in this way?&amp;nbsp; Also, since the user manual says that the read data is sampled with a n internally generated, 1/4 cycle delayed clock, does that impact the timing specs in the datasheet which only reference MEMCLK?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 06 Apr 2015 15:27:24 GMT</pubDate>
    <dc:creator>patrickgillespi</dc:creator>
    <dc:date>2015-04-06T15:27:24Z</dc:date>
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      <title>MPC5200 SDRAM timing clarification</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5200-SDRAM-timing-clarification/m-p/380084#M486</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;On the MPC5200 SDRAM timing, standard SDRAM, read timing, the data setup is specified as a max of 0.3ns.&amp;nbsp; Normalli I see setup time specified as minimums.&amp;nbsp; Is this an error, or is there any clarification of why this is specified in this way?&amp;nbsp; Also, since the user manual says that the read data is sampled with a n internally generated, 1/4 cycle delayed clock, does that impact the timing specs in the datasheet which only reference MEMCLK?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Apr 2015 15:27:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5200-SDRAM-timing-clarification/m-p/380084#M486</guid>
      <dc:creator>patrickgillespi</dc:creator>
      <dc:date>2015-04-06T15:27:24Z</dc:date>
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