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    <title>topic Re: MPC5784G Memory Protection issue: in MPC5xxx</title>
    <link>https://community.nxp.com/t5/MPC5xxx/MPC5784G-Memory-Protection-issue/m-p/577419#M4134</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;To distinguish between tasks on singlecore you can use PID.You can configure several descriptors covering the same address space, so you can assign different access rights for different PIDs.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Multicore:&lt;/P&gt;&lt;P&gt;It is possible to configure several descriptors and access rights separately for each master (using word2 in descriptor).&lt;/P&gt;&lt;P&gt;Additionally you have two levels of accesses based on MasterID and PID. Which gives you freedom to grant/deny accesses to memory regions for multicore.&lt;/P&gt;&lt;P&gt;Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 18 Aug 2016 07:21:33 GMT</pubDate>
    <dc:creator>petervlna</dc:creator>
    <dc:date>2016-08-18T07:21:33Z</dc:date>
    <item>
      <title>MPC5784G Memory Protection issue:</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5784G-Memory-Protection-issue/m-p/577416#M4131</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We are using MPC5748G and implemented memory protection for SMPU0 and SMPU1 using PID. In that we have provided two modes, one is Supervisory mode and another is user mode. &lt;BR /&gt;In supervisory mode we are providing full access to SMPU0 and SMPU1 address range with fixed PID. In user mode we are providng limited access to SMPU0 and SMPU1 address range &lt;BR /&gt;depends on PID set for that application. Now we want to limit the access of some section of SMPU1 address range in Supervisory Mode&amp;nbsp; for Some function and SMPU0 has full access , but we are facing some issues in accessing as PID is common for &lt;BR /&gt;SMPU0 and SMPU1 address range. Following example will explain the issue.&lt;/P&gt;&lt;P&gt;Example.&lt;BR /&gt;Mode: Supervisory&lt;BR /&gt;PID: 0XFF&lt;BR /&gt;SMPU0 Address range : &lt;BR /&gt;Start Address: 0x00000000&lt;BR /&gt;End Address:&amp;nbsp;&amp;nbsp; 0x3FFFFFFF&lt;BR /&gt;PID : 0XFF&lt;/P&gt;&lt;P&gt;Peripheral Access:&lt;BR /&gt;Start Address: 0xF0000000&lt;BR /&gt;End Address:&amp;nbsp;&amp;nbsp; 0xFFFFFFFF&lt;BR /&gt;PID : 0XFF&lt;/P&gt;&lt;P&gt;SMPU1 Address range:&lt;BR /&gt;Start Address: 0x4000F000&lt;BR /&gt;End Address:&amp;nbsp;&amp;nbsp; 0x400BFFFF&lt;BR /&gt;PID : 0XFF&lt;/P&gt;&lt;P&gt;Limited access block :&lt;BR /&gt;Start Address: 0x40000000&lt;BR /&gt;End Address:&amp;nbsp;&amp;nbsp; 0x4000EFFF&lt;BR /&gt;PID : 0X0F&lt;/P&gt;&lt;P&gt;Now In supervisory mode Fun_1() should have full access to All memory range and Fun_2() should have acess to all blocks except Limited access block.&lt;BR /&gt;As in hardware only one register 48 is provided for accessing regions. We tried it but facing issues in accessing SMPU0 as PID set for region is 0XFF.&lt;BR /&gt;Is it possible to provide this kind of access? Plese let us know more information on the same issue. &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Aug 2016 08:27:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5784G-Memory-Protection-issue/m-p/577416#M4131</guid>
      <dc:creator>bhagyashriratho</dc:creator>
      <dc:date>2016-08-08T08:27:39Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5784G Memory Protection issue:</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5784G-Memory-Protection-issue/m-p/577417#M4132</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #0070c0;"&gt;[Peter] – In this case you need to:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #0070c0;"&gt;Do not use PID (disable it) for all access blocks. Use it only for limited access block.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Mode: Supervisory&lt;BR /&gt; PID: -dissable&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; SMPU0 Address range : &lt;BR /&gt; Start Address: 0x00000000&lt;BR /&gt; End Address:&amp;nbsp;&amp;nbsp; 0x3FFFFFFF&lt;BR /&gt; PID: -dissable&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Peripheral Access:&lt;BR /&gt; Start Address: 0xF0000000&lt;BR /&gt; End Address:&amp;nbsp;&amp;nbsp; 0xFFFFFFFF&lt;BR /&gt; PID: -dissable&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;SMPU1 Address range:&lt;BR /&gt; Start Address: 0x4000F000&lt;BR /&gt; End Address:&amp;nbsp;&amp;nbsp; 0x400BFFFF&lt;BR /&gt; PID: -dissable&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Limited access block :&lt;BR /&gt; Start Address: 0x40000000&lt;BR /&gt; End Address:&amp;nbsp;&amp;nbsp; 0x4000EFFF&lt;BR /&gt; PID : 0X0F - enable&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 16 Aug 2016 13:42:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5784G-Memory-Protection-issue/m-p/577417#M4132</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2016-08-16T13:42:42Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5784G Memory Protection issue:</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5784G-Memory-Protection-issue/m-p/577418#M4133</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your reply. The solution which you have provided is possible in case of Single core. In case of multicore it will not possible, as functionality of multicore handled individually.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For example:&lt;/P&gt;&lt;P&gt;On core 0 Fun1() is running in supervisory mode.&lt;/P&gt;&lt;P&gt;On core1 Fun2() is running with limited access mode/user mode&lt;/P&gt;&lt;P&gt;On core2 Fun3() is running with limited access mode/user mode&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If I have disable PID of Supervisory block then Fun2() and Fun3() can able to access the memory. Fun2() and Fun3() might be corrupt the memory. So in this case How can I manage this problem.&lt;/P&gt;&lt;P&gt;Please let us know the solution for same issue with multicore functionality.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bhagyashri Rathod&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 17 Aug 2016 06:59:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5784G-Memory-Protection-issue/m-p/577418#M4133</guid>
      <dc:creator>bhagyashriratho</dc:creator>
      <dc:date>2016-08-17T06:59:20Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5784G Memory Protection issue:</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5784G-Memory-Protection-issue/m-p/577419#M4134</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;To distinguish between tasks on singlecore you can use PID.You can configure several descriptors covering the same address space, so you can assign different access rights for different PIDs.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Multicore:&lt;/P&gt;&lt;P&gt;It is possible to configure several descriptors and access rights separately for each master (using word2 in descriptor).&lt;/P&gt;&lt;P&gt;Additionally you have two levels of accesses based on MasterID and PID. Which gives you freedom to grant/deny accesses to memory regions for multicore.&lt;/P&gt;&lt;P&gt;Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 Aug 2016 07:21:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5784G-Memory-Protection-issue/m-p/577419#M4134</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2016-08-18T07:21:33Z</dc:date>
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