mpc5748g enet d-cache

tomyqg — Mon, 01 Aug 2016 14:07:20 GMT

Hi, everyone!

How to configure the D-cache for memory and put the enet Rx Description and Tx Description in the un-cachable memory space on MPC5748G?

Re: mpc5748g enet d-cache

lukaszadrapa — Tue, 02 Aug 2016 12:41:35 GMT

Hi,

data cache can be enabled in this way:

__dcache_cfg:

e_li r5, 0x2

mtspr 1010,r5

e_li r7, 0x4

e_li r8, 0x2

e_lis r11,0xFFFF

e_or2i r11,0xFFFB

__dcache_inv:

mfspr r9, 1010

and. r10, r7, r9

e_beq __dcache_no_abort

and. r10, r11, r9

mtspr 1010, r10

e_b __icache_cfg

__dcache_no_abort:

and. r10, r8, r9

e_bne __dcache_inv

mfspr r5, 1010

e_ori r5, r5, 0x0001

se_isync

msync

mtspr 1010, r5

If you want to configure certain address space as cache inhibited, use SMPU module. Simple example for SMPU configuration can be found here:

"Cache Inhibit" bit CI can be found in Word 3 of the descriptor (register SMPUx_RGDn_WRD3).

Regards,

Lukas

tomyqg — Thu, 04 Aug 2016 14:31:48 GMT

Thank you very much, SMPU is the point!