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    <title>topic Re: MPC5748G MII_Lite in MPC5xxx</title>
    <link>https://community.nxp.com/t5/MPC5xxx/MPC5748G-MII-Lite/m-p/529710#M3545</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;No ENET setting is needed. Just pins should be handled accordingly.&lt;/P&gt;&lt;P&gt;See chapter 2.1 “MII versus MII-Lite” of the AN4577; &lt;A href="http://www.nxp.com/files/32bit/doc/app_note/AN4577.pdf"&gt;http://www.nxp.com/files/32bit/doc/app_note/AN4577.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;It is written for the FEC module, but can be reused on MPC5748G too.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, Petr &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 22 Jul 2016 11:50:36 GMT</pubDate>
    <dc:creator>PetrS</dc:creator>
    <dc:date>2016-07-22T11:50:36Z</dc:date>
    <item>
      <title>MPC5748G MII_Lite</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5748G-MII-Lite/m-p/529709#M3544</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm looking for the setting to enable the MII_Lite mode of Ethernet controller on the Calypso.&amp;nbsp; COL, RX_ER and CRS signals are not available on our design.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I've found any information is MPC5748G_RM v3 about making&amp;nbsp; Ethernet controller ignoring theses signals.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Jul 2016 09:53:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5748G-MII-Lite/m-p/529709#M3544</guid>
      <dc:creator>AROK</dc:creator>
      <dc:date>2016-07-22T09:53:45Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5748G MII_Lite</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5748G-MII-Lite/m-p/529710#M3545</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;No ENET setting is needed. Just pins should be handled accordingly.&lt;/P&gt;&lt;P&gt;See chapter 2.1 “MII versus MII-Lite” of the AN4577; &lt;A href="http://www.nxp.com/files/32bit/doc/app_note/AN4577.pdf"&gt;http://www.nxp.com/files/32bit/doc/app_note/AN4577.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;It is written for the FEC module, but can be reused on MPC5748G too.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR, Petr &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Jul 2016 11:50:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5748G-MII-Lite/m-p/529710#M3545</guid>
      <dc:creator>PetrS</dc:creator>
      <dc:date>2016-07-22T11:50:36Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5748G MII_Lite</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5748G-MII-Lite/m-p/529711#M3546</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;That true for the MPC564xB-C.&amp;nbsp; &lt;/P&gt;&lt;P&gt;With the Calypso,&amp;nbsp; the MAC is supposed to support MII_Lite. More than this when both ethernet controller are used the COL pin is no longer available because it used for the second MII bus.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Rem: I'm trying to get some answers from my contact at NXP &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 22 Jul 2016 12:06:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5748G-MII-Lite/m-p/529711#M3546</guid>
      <dc:creator>AROK</dc:creator>
      <dc:date>2016-07-22T12:06:51Z</dc:date>
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