topic Re: MPC5775K SEMA42 multi cores in MPC5xxx

MPC5775K SEMA42 multi cores

ronliu — Sun, 12 Jun 2016 12:14:17 GMT

Hi, Martin Kovar Petr Stancik Stanislav Sliva

I'm trying to debug to SEMA42 module in the MPC5775K. I'd like to make one core to communicate with other. Is there some sample codes to share? Thanks.

Regards,

Ron

Re: MPC5775K SEMA42 multi cores

ronliu — Mon, 13 Jun 2016 08:49:53 GMT

And when I try to lock the gate. IVOR1_Vector() appears.

Then I could not trace it by the IDE.

Re: MPC5775K SEMA42 multi cores

martin_kovar — Mon, 13 Jun 2016 11:41:54 GMT

Hi Ron,

please look at the following example. I tested it with PeMicro debug probe in S32DS and I did not get any IVOR exception.

Example MPC5775K Semaphores S32DS

What do you mean by communication between cores? If you want to send messages from one core to another, you can use shared memory. For this purpose the example mentioned above is also usable.

If you have any other question, please feel free to write me back.

Regards,

Martin

Re: MPC5775K SEMA42 multi cores

ronliu — Tue, 14 Jun 2016 07:26:13 GMT

Hi Martin,

Thanks. You are right. I'd like to send messages from one core to another. And I have tested your example. Following what you said, I modified the mem.ld and section.ld. But there are still some parts in your example I could not understand. Please pay attention to the red lines.

In the core0,

In the core1,

My project is that the core0 gets commands from CAN bus and then core0 sends the commands to core1 through shared memory. I'm not clear how to lock and unlock cores.

The problem is that I could not read the correct data in the core1.

Regards,

Ron

Re: MPC5775K SEMA42 multi cores

martin_kovar — Tue, 14 Jun 2016 08:31:59 GMT

Hi Ron,

the general (simplified) principle of using semaphores is following:

You have two cores, one shared resource (for example memory) and one gate, which protects the shared resource. If any core wants to access to the shared resource, it has to check, of the gate is unlocked. If yes, core locks the gate and uses the shared resource (this is called critical section). After core leaves critical section (does not want to work shared resource anymore), core has to unlock the gate (because of deadlock) and any other core can use it now.

If the gate is locked, core has to wait, until other core unlock it. Gate can be unlock only by the the core which locked it.

And lets look at the example.

1)what do you mean about status? which core?

Status variable determines the status of the GATE (only gate 0 is used for both cores). If gate is unlock, core can lock it and execute it's critical section (access to shared resource).

2) status = Get_Gate_Status(GATE0 or GATE1)?

In this example only one gate is used, because there is only one shared resource. So the answer is GATE0. This is also answer for your next question.

3) Read shared memory here?

Yes, after you lock the gate, you are in the critical section and you can use (read/write) shared resource. Just realize, which operations are mutual.

read/read - not mutual...more cores can access shared resource

write/read - mutual exclusion

write/write - mutual exclusion

About the use case you describe I do not understand much, but I suppose you have some array called CanCMD[8]. If you want to write to this array, core0 should lock the gate0 and write to the array, then unlock the gate. Core1 has to wait, until gate0 is unlocked. Then core1 locks the gate, reads data from array and unlocks the gate.

Check in the debugger, if memcpy function copies correct data to the correct address and also if pcmd points to correct address.

Regards,

Martin

Re: MPC5775K SEMA42 multi cores

ronliu — Tue, 14 Jun 2016 10:09:00 GMT

Thanks Martin,

I found that it was running correctly if I just only locked and unlocked the gate 0. As the picture shows,

But if I tried to read or write data in the shared memory. The project jumped into the IVOR1_Vector(). So I doubt that if there is something wrong with the configuration about link files.

1. This is the configuration about mem.ld.

My project is that each core gets 128K * 3 = 384K RAM. The rest 128K is used as shared memory.

CORE0 0x40000000 ~ 0x4005FFFF

CORE1 0x40060000 ~ 0x400BFFFF

CORE2 0x400C0000 ~ 0x4011FFFF

SHARED 0x40120000 ~ 0x4013FFFF

2. I added the parts between red lines in every sections.ld.

3. The shared memory structure is like that. There are 8 bytes in it. The total size of shared memory is 128K. But I only use 8 bytes now. I think it is not important.

In the first core, I create a new structure in the shared memory and write some new data to 'gCANCmd'.

Then I declare the shared memory in the second core and read data from '_shared_mem[]'

Especially， I really lock and unlocked the GATE_0 when I try to execute the process of reading and writing.

So the problem is why it goes wrong when I am using the shared memory. Any ideas?

Regards,

Ron

Re: MPC5775K SEMA42 multi cores

martin_kovar — Tue, 14 Jun 2016 10:40:01 GMT

Hi Ron,

from the screens you sent me it seems, linker file is OK. Is it possible for you to share your project here? I need to check the whole code.

Regards,

Martin

Re: MPC5775K SEMA42 multi cores

ronliu — Tue, 14 Jun 2016 12:51:05 GMT

Hi Martin,

I create a new project. It has the sample problem. I'm confused that I don't know how to upload the code file in the NXP community. So I upload it to the Baidu cloud disk. I'm not sure whether you can download or not.

http://pan.baidu.com/s/1kVpRPOF

My personal email address is ron.liu@live.com. If you have any problem to get it. Please send me an email. I will send it to you as an attach again.

Regards,

Ron

Re: MPC5775K SEMA42 multi cores

martin_kovar — Tue, 14 Jun 2016 13:30:42 GMT

Hi Ron,

you do not have initialized the shared RAM. Each core initialize only 384K. Please edit mem.ld file for z4 core. Use the following code SRAM_SIZE = 1280K; instead of SRAM_SIZE = 384K;

Now it should works.

Regards,

Martin

Re: MPC5775K SEMA42 multi cores

ronliu — Wed, 15 Jun 2016 03:24:58 GMT

Hi, Martin,

I modified the mem.ld for z4. And it works now. It no longer jump to the IVOR1_Vector(). However there is still a problem. The data is been refreshing all the time in the core0, but I couldn't get the updated data in the core1. In other words, I'm able to see the changing data in core0 and constant data in core1 in the watching windows. Is it the right way to read data in the picture below?

And I upload the new project in the cloud disk. You may download and debug it. http://pan.baidu.com/s/1c1RJ8Qk .

Thanks again.

Ron

Re: MPC5775K SEMA42 multi cores

martin_kovar — Wed, 15 Jun 2016 05:59:02 GMT

Hi Ron,

please use the advanced editor feature. There is option attach, which could be used to upload your projects.

Regards,

Martin

Re: MPC5775K SEMA42 multi cores

ronliu — Wed, 15 Jun 2016 06:17:35 GMT

Hi Martin,

Thanks for your tips. The attach is the newest project. Could you please help to debug it?

Regards,

Ron

Re: MPC5775K SEMA42 multi cores

martin_kovar — Wed, 15 Jun 2016 08:13:01 GMT

Hi Ron,

This problem you describe is caused by cache memory. You should disable cache memory or use SMPU to inhibit shared RAM to be cached.

Regards,

Martin

Re: MPC5775K SEMA42 multi cores

ronliu — Wed, 15 Jun 2016 08:55:09 GMT

What should I do to disable DCache? I tried to call this function. But there are a lot of errors.

Re: MPC5775K SEMA42 multi cores

martin_kovar — Wed, 15 Jun 2016 10:21:00 GMT

Hi Ron,

in startup files, comment the piece of the code, which enable cache memory.

Regards,

Martin

Re: MPC5775K SEMA42 multi cores

ronliu — Wed, 15 Jun 2016 13:13:01 GMT

Martin,

I modified these three startup.s. But the problem still existed. Is it the right way to comment lines about the cache?

Regards,

Ron

Re: MPC5775K SEMA42 multi cores

martin_kovar — Thu, 16 Jun 2016 05:59:11 GMT

Hi Ron,

yes, the comment you used is correct. Cache is disabled now. But I worry about the debugger. I tried to use PEMicro debug probe and S32DS debugger and debug your project, but it was nearly impossible.

When I had tried any simpler project (for example the project I shared here) it worked correct. In the end, I tried to debug your project using Lauterbach debugger and it worked correct when I disabled cache.

Regards,

Martin

Re: MPC5775K SEMA42 multi cores

ronliu — Thu, 16 Jun 2016 08:33:05 GMT

Martin,

Thank you all the same. Do you know it is OK to debug MPC5775K multi-cores project in GHS IDE?

Regards,

Ron

Re: MPC5775K SEMA42 multi cores

ronliu — Thu, 16 Jun 2016 08:40:59 GMT

There is still a doubt. If I download the firmware rather than using the S32 debugger. Could it be able to run correctly?

Re: MPC5775K SEMA42 multi cores

martin_kovar — Thu, 16 Jun 2016 11:13:26 GMT

Hi Ron,

I do not have any experience with GHS IDE so I am not tell you any relevant information. I also do not know if it is possible to use PEMicro debug probe with GHS IDE.

About your second question, I do not know what you mean by firmware.

But there is one possible way, which could be suitable for you. At the end of June, S32DS v 1.1 should be released and I hope, there will be fixed some bugs in debugger and it will become more usable for complex projects.

The best way, how to debug more complex project is Lauterbach debugger, but I know that the price is high.

Regards,

Martin