https://community.nxp.com/t5/MPC5xxx/What-should-PortPinSlewRate-be-configured-for-SPI-pins-NXP-MCAL/m-p/2256996#M28226 <P>Hello,</P> <DIV> <P>What does PortPinSlewRate do?</P> <UL> <LI>It controls how fast the pin transitions between logic levels (rise/fall time).</LI> <LI>Options typically include: <UL> <LI>FullDriveWithoutSlewRate (fastest switching, no slew rate limitation)</LI> <LI>Slow or Medium slew rate (adds delay to reduce EMI and ringing)</LI> <LI>Sometimes called Slew Rate Enabled/Disabled in hardware registers.</LI> </UL> </LI> </UL> <P>NXP’s Recommendation for SPI Pins</P> <P>For high-speed interfaces like SPI (SCK, MOSI, MISO, CS), NXP generally recommends:</P> <UL> <LI>Disable slew rate limitation (i.e., use FullDriveWithoutSlewRate) for reliable high-speed communication.</LI> <LI>Reason: Slew rate limiting can distort edges and cause timing violations at higher SPI baud rates, leading to data corruption.</LI> <LI>This is consistent with the hardware default: SRE = 0 → fast slew rate on most NXP MCUs.</LI> </UL> <P>Why did your tests confirm this?</P> <UL> <LI>When you used FullDriveWithoutSlewRate, the SPI signals had sharp edges, meeting timing requirements.</LI> <LI>With slower slew rates, the rise/fall times increased, causing setup/hold violations and corruption.</LI> </UL> <P>Official Guidance</P> <UL> <LI>NXP community and application notes indicate that for SPI and other high-speed signals, fast slew rate (no limitation) is preferred.</LI> <LI>Slower slew rates are mainly for GPIO or low-frequency signals to reduce EMI, not for SPI</LI> </UL> <P>Best regards,</P> <P>Peter</P> </DIV> Mon, 08 Dec 2025 08:47:58 GMT petervlna 2025-12-08T08:47:58Z https://community.nxp.com/t5/MPC5xxx/What-should-PortPinSlewRate-be-configured-for-SPI-pins-NXP-MCAL/m-p/2256140#M28223 <P>Hi,<BR />I am using NXP MCAL 4.2.2 and configuring SPI communication with an external slave device.<BR />In the Port configuration, there is a parameter called PortPinSlewRate.</P><P>For SPI pins (SCK, MOSI, MISO, CS), what is the recommended value for PortPinSlewRate?</P><P>In my testing, I am observing data corruption in all modes except when PortPinSlewRate is configured as FullDriveWithoutSlewRate.<BR />I want to confirm what NXP officially recommends for SPI communication.</P><P>Thanks.</P> Fri, 05 Dec 2025 12:43:47 GMT https://community.nxp.com/t5/MPC5xxx/What-should-PortPinSlewRate-be-configured-for-SPI-pins-NXP-MCAL/m-p/2256140#M28223 AkshayNaik1907 2025-12-05T12:43:47Z https://community.nxp.com/t5/MPC5xxx/What-should-PortPinSlewRate-be-configured-for-SPI-pins-NXP-MCAL/m-p/2256996#M28226 <P>Hello,</P> <DIV> <P>What does PortPinSlewRate do?</P> <UL> <LI>It controls how fast the pin transitions between logic levels (rise/fall time).</LI> <LI>Options typically include: <UL> <LI>FullDriveWithoutSlewRate (fastest switching, no slew rate limitation)</LI> <LI>Slow or Medium slew rate (adds delay to reduce EMI and ringing)</LI> <LI>Sometimes called Slew Rate Enabled/Disabled in hardware registers.</LI> </UL> </LI> </UL> <P>NXP’s Recommendation for SPI Pins</P> <P>For high-speed interfaces like SPI (SCK, MOSI, MISO, CS), NXP generally recommends:</P> <UL> <LI>Disable slew rate limitation (i.e., use FullDriveWithoutSlewRate) for reliable high-speed communication.</LI> <LI>Reason: Slew rate limiting can distort edges and cause timing violations at higher SPI baud rates, leading to data corruption.</LI> <LI>This is consistent with the hardware default: SRE = 0 → fast slew rate on most NXP MCUs.</LI> </UL> <P>Why did your tests confirm this?</P> <UL> <LI>When you used FullDriveWithoutSlewRate, the SPI signals had sharp edges, meeting timing requirements.</LI> <LI>With slower slew rates, the rise/fall times increased, causing setup/hold violations and corruption.</LI> </UL> <P>Official Guidance</P> <UL> <LI>NXP community and application notes indicate that for SPI and other high-speed signals, fast slew rate (no limitation) is preferred.</LI> <LI>Slower slew rates are mainly for GPIO or low-frequency signals to reduce EMI, not for SPI</LI> </UL> <P>Best regards,</P> <P>Peter</P> </DIV> Mon, 08 Dec 2025 08:47:58 GMT https://community.nxp.com/t5/MPC5xxx/What-should-PortPinSlewRate-be-configured-for-SPI-pins-NXP-MCAL/m-p/2256996#M28226 petervlna 2025-12-08T08:47:58Z