MPC5xxxのトピックRe: ECC Monitoring Enable for AXBS, Flash and RAM Array on MPC5746C

ECC Monitoring Enable for AXBS, Flash and RAM Array on MPC5746C

NileshDharap — Wed, 06 Aug 2025 11:00:06 GMT

Hello,
I am working on a software safety requirement where ECC detection must be enabled on AXBS crossbar, Flash array, RAM array, DMA RAM, and FlexRay RAM.

For DMA RAM and FlexRay RAM, we found ECC-related control bits in registers DMA_ES and FR_MCR (see attached screenshots).

However, we couldn't find similar control bits for AXBS, Flash array, and RAM array in the MPC5746C reference manual.
Is ECC detection and correction enabled by default for AXBS, Flash and RAM arrays on MPC5746C?
Or is there any specific way or register to enable ECC for these?

Thanks in advance.
Nilesh

Re: ECC Monitoring Enable for AXBS, Flash and RAM Array on MPC5746C

petervlna — Wed, 06 Aug 2025 11:46:33 GMT

Hello,

1. AXBS (Crossbar Switch)

End-to-End ECC (e2eECC) is supported across all bus masters and interconnects.
ECC is enabled by default for transactions through AXBS, ensuring data integrity from source to destination

2. Flash Memory

ECC is enabled by default for Flash memory.
The C55FMC (Flash Memory Controller) handles ECC generation and checking.
Single-bit errors are automatically corrected, while multi-bit errors are detected and reported to the ERM/MEMU modules

3. RAM Arrays

ECC support is available for internal SRAM and enabled by default.
ECC configuration for RAM is typically done via ERM (Error Reporting Module) or MEMU (Memory Error Management Unit) registers.

best regards,

Peter

Re: ECC Monitoring Enable for AXBS, Flash and RAM Array on MPC5746C

NileshDharap — Thu, 07 Aug 2025 05:45:00 GMT

Thanks for the quick reply, Peter

Re: ECC Monitoring Enable for AXBS, Flash and RAM Array on MPC5746C

mayank22 — Mon, 22 Sep 2025 09:22:35 GMT

Hi Peter,

For the same topic I am trying to implement an interrupt based method to Monitor ECC for DMA via DMA_ES[UCE]. from our conversation we know that ECC for DMA is enabled by default. Now here is the issue , its a read only bit,

The DMA_ES.UCE bit is set automatically by the eDMA hardware when an uncorrectable ECC error occurs during channel execution, as described in section 68.4.2 of the manual.

To verify the behavior of DMA_ES.UCE, we need to manipulate the eDMA system to create an error scenario, such as corrupting the TCD memory. Is there any way to achieve this results where we can get the ECC bit set as we introduce the error. if so what can be approach to do so ?