MPC5xxx中的主题 Re: Disabling MPC5777C (remaining) data cache while keeping its stack there

Disabling MPC5777C (remaining) data cache while keeping its stack there

ricardofranca — Tue, 25 Feb 2025 11:47:09 GMT

Hello,

I am following AN5191 guidance to boot a MPC5777C custom board and some of its built-in tests require me to disable the caches to perform some actions, then re-enable them for normal operation. Considering that I took half of the data cache to be my stack (using the AN5191 code based on dcbz and dcbtls instructions), how should I proceed to keep the stack working while disabling the rest of the data cache?

Thanks,

Ricardo

Re: Disabling MPC5777C (remaining) data cache while keeping its stack there

davidtosenovjan — Wed, 26 Feb 2025 12:42:06 GMT

The ICINV/DCINV Flash invalidation invalidates ALL cache, locked lines are also invalidated using this, but ICLFC/DCLFC will not be altered by the invalidation action, so to clear the Lock Bits the software must write this bit. You will end up with an invalid line which is locked if you just do the invalidate operation with this register.

The icbi cache instructions invalidates and unlocks a cache lines in the L1 ICache.

Pay attention to following presentation, slides 115-139, showing detailed description of cache instructions and also some code examples:

https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/e200-Core-Training-relevant-to-MPC55xx-and-MPC56xx-device-family/ta-p/1115124

Re: Disabling MPC5777C (remaining) data cache while keeping its stack there

ricardofranca — Thu, 06 Mar 2025 19:53:41 GMT

Hello David,

Is it possible to use L1FINV0[CCMD] to force CWAY to 0 for a 4KB stack? I was thinking about something like:

stack_cache_0: mfpir r3 se_cmpi r3,0 se_bne stack_cache_1 /* this part is Core 0 only */ /* assuming a 4KB stack */ e_li r4,3 # will set L1FINV0[CWAY] = 0 and L1FINV0[CCMD] = 3 e_lis r5,__CPU0_STACK_SIZE@h e_or2i r5,__CPU0_STACK_SIZE@l se_srwi r5,5 # Shift the contents of R3 right by 5 bits (stack_size/32 = 128) se_mtctr r5 e_lis r3,_cpu0_stack_end@h e_or2i r3,_cpu0_stack_end@l mtl1finv0 r4 lock_cache_loop_cpu0_way0: dcbz r0,r3 # Establish address in cache for 32 bytes and zero dcbtls 0,r0,r3 # Lock the address into the cache se_addi r3,32 # Increment to start of next cache line (+32 bytes) e_bdnz lock_cache_loop_cpu0_way0 # Decrement the counter (CTR), branch if nonzero

But I don't know how to be sure my stack is where I think it is.

Thanks!

Re: Disabling MPC5777C (remaining) data cache while keeping its stack there

davidtosenovjan — Fri, 07 Mar 2025 14:26:10 GMT

At init, it is supposed to invalidate all. It also forces replacement counter to way 0. Then you may lock lines for cache.

Re: Disabling MPC5777C (remaining) data cache while keeping its stack there

ricardofranca — Mon, 10 Mar 2025 13:15:08 GMT

Hi David,

Am I right to assume that if I set L1FINV0[CCMD] to 3, it will force the way replacement counter to the value I specify in L1FINV0[CWAY] without performing any flush/invalidation?

Thanks!

Re: Disabling MPC5777C (remaining) data cache while keeping its stack there

davidtosenovjan — Mon, 10 Mar 2025 13:28:53 GMT

I can neither confirm nor deny this. It doesn't come out of any description.

Re: Disabling MPC5777C (remaining) data cache while keeping its stack there

ricardofranca — Mon, 10 Mar 2025 23:28:44 GMT

I thought this use of L1FINV0 would not invalidate anything because the description of L1FINV0[CCMD] provides details of invalidation/flushing for all cache commands except this one:

In any case, what happens if I try to invalidate a locked cache line?

Thanks!

Re: Disabling MPC5777C (remaining) data cache while keeping its stack there

davidtosenovjan — Tue, 11 Mar 2025 08:27:51 GMT

I see. You are right apparently.

The icbi cache instructions invalidates and unlocks a cache lines in the L1 ICache.