DSPIx_POPR error

shenrwszai — Tue, 24 Dec 2024 08:27:22 GMT

/* main.c: performs a single transfer from DSPI_C to DSPI_D on MPC555x*/
/* Rev 1.0 Sept 14 2004 S.Mihalik */
/* Rev 2.0 Jan 3 2007 S. Mihalik - Modified to use two SPIs */
/* Rev 2.1 July 20 2007 SM - Modified for MPC551x, changed sysclk (50 MHz) */
/* Rev 2.2 Aug 13 2007 SM - Modified for sysclk of 64 MHz & lenghened CSSCK, ASC*/
/* Rev 2.3 Jun 04 2008 SM - initSysclk changed for MPC5633M support */
/* Rev 2.4 Aug 15 2008 SM - removed lines for MPC551x, MPC563x */
/* Rev 2.5 Aug 18 2008 D McKenna- Kept DSPI_MCR[HALT] set during initialization*/
/* Copyright Freescale Semiconductor, Inc. 2007 All rights reserved. */
/* Notes: */
/* 1. MMU not initialized; must be done by debug scripts or BAM */
/* 2. SRAM not initialized; must be done by debug scripts or in a crt0 type file */

#include "mpc5554.h" /* Use proper include file like mpc5510.h or mpc5554.h */

vuint32_t i = 0; /* Dummy idle counter */
uint16_t RecDataMaster = 0; /* Data recieved on master SPI */
uint16_t RecDataSlave = 0; /* Data received on slave SPI */

void initSysclk (void) {
FMPLL.SYNCR.R = 0x16080000; /* 8 MHz xtal: 0x16080000; 40MHz: 0x46100000 */
while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK */
FMPLL.SYNCR.R = 0x16000000; /* 8 MHz xtal: 0x16000000; 40MHz: 0x46080000 */
}

void initDSPI_C(void) {
DSPI_C.MCR.R = 0x80010001; /* Configure DSPI_C as master */
DSPI_C.CTAR[0].R = 0x780A7727; /* Configure CTAR0 */
DSPI_C.MCR.B.HALT = 0x0; /* Exit HALT mode: go from STOPPED to RUNNING state*/
SIU.PCR[107].R = 0x0A00; /* MPC555x: Config pad as DSPI_C SOUT output */
SIU.PCR[108].R = 0x0900; /* MPC555x: Config pad as DSPI_C SIN input */
SIU.PCR[109].R = 0x0A00; /* MPC555x: Config pad as DSPI_C SCK output */
SIU.PCR[110].R = 0x0A00; /* MPC555x: Config pad as DSPI_C PCS0 output */
}

void initDSPI_D(void) {
DSPI_D.MCR.R = 0x00010001; /* Configure DSPI_D as slave */
DSPI_D.CTAR[0].R = 0x780A7727; /* Configure CTAR0 */
DSPI_D.MCR.B.HALT = 0x0; /* Exit HALT mode: go from STOPPED to RUNNING state*/
SIU.PCR[98].R = 0x0900; /* MPC555x: Config pad as DSPI_D SCK input */
SIU.PCR[99].R = 0x0900; /* MPC555x: Config pad as DSPI_D SIN input */
SIU.PCR[100].R = 0x0A00; /* MPC555x: Config pad as DSPI_D SOUT output*/
SIU.PCR[106].R = 0x0900; /* MPC555x: Config pad as DSPI_D PCS0/SS input */
}

void ReadDataDSPI_D(void) {
while (DSPI_D.SR.B.RFDF != 1){} /* Wait for Receive FIFO Drain Flag = 1 */
RecDataSlave = DSPI_D.POPR.R; /* Read data received by slave SPI */
DSPI_D.SR.R = 0x80020000; /* Clear TCF, RDRF flags by writing 1 to them */
}

void ReadDataDSPI_C(void) {
while (DSPI_C.SR.B.RFDF != 1){} /* Wait for Receive FIFO Drain Flag = 1 */
RecDataMaster = DSPI_C.POPR.R; /* Read data received by master SPI */
DSPI_C.SR.R = 0x90020000; /* Clear TCF, RDRF, EOQ flags by writing 1 */
}

int main(void) {
SIU.DISR.R = 0x0000C0FC; /* MPC555x only: Connect DSPI_C, DSPI_D internally */
initSysclk(); /* Set sysclk = 64MHz running from PLL */
initDSPI_C(); /* Initialize DSPI_C as master SPI and init CTAR0 */
initDSPI_D(); /* Initialize DSPI_D as Slave SPI and init CTAR0 */
DSPI_D.PUSHR.R = 0x00001234; /* Initialize slave DSPI_D's response to master */
DSPI_C.PUSHR.R = 0x08015678; /* Transmit data from master to slave SPI with EOQ */
ReadDataDSPI_D(); /* Read data on slave DSPI */
ReadDataDSPI_C(); /* Read data on master DSPI */
while (1) {i++; } /* Wait forever */
}

1): Why is the value of RecDataMaster not DSPI_C.POPR.R ?

2): Why doesn't this line of code work？

DSPI_D.SR.R = 0x80020000; /* Clear TCF, RDRF flags by writing 1 to them */

DSPI_C.SR.R = 0x90020000; /* Clear TCF, RDRF, EOQ flags by writing 1 */

Re: DSPIx_POPR error

PetrS — Thu, 02 Jan 2025 07:36:50 GMT

Hi,

could you be more specific for both points?
If DSPIs are interconnected then running this code you should see
1) RecDataMaster = 0x1234
2) respective flags cleared in SR registers

BR, Petr

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