topic Re: MPC5746B trapping by IVOR1_Vector in MPC5xxx

MPC5746B trapping by IVOR1_Vector

karma_JC — Mon, 16 Oct 2023 16:01:08 GMT

Hi:

I need some help on IVOR1_Vector trap when I initiate DSPI interface by calling DSPI_MasterInit -> DSPI_Set_MCR_HALT. After that, it is trapped in IVOR1_Handler(Machine Check Interrupt). Would you know what is the cause of this issue?????

Thank you

James

Re: MPC5746B trapping by IVOR1_Vector

petervlna — Tue, 17 Oct 2023 07:23:37 GMT

Hello,

Would you know what is the cause of this issue?????

Have a look at core reference manual to understand the root cause:

Best regards,

Peter

Re: MPC5746B trapping by IVOR1_Vector

karma_JC — Wed, 18 Oct 2023 21:45:25 GMT

Hi Peter:

Thanks for the advice. I found chapter 63 of MPC5476 B/C/G RM contained the information regarding MCSR register.

I'm assuming from S32D Studio shall be able to view this register from debug mode. However, I was not able to view this MSCR register under "register" list; I only saw MSR register. Would you please provide some info on how to access MSCR register from debugger?

Thank you

James

Re: MPC5746B trapping by IVOR1_Vector

petervlna — Thu, 19 Oct 2023 08:04:58 GMT

Hello,

I am not using S32DS interface for debug, but I found that you can view them via SPR registers:

Best regards,

Peter

Re: MPC5746B trapping by IVOR1_Vector

karma_JC — Mon, 23 Oct 2023 18:12:05 GMT

Hi Peter:

Thank you for the guide for finding the MCSR register under SPR.

The following is the snapshot of the MCSR related registers when the exception was taking place:

It seems to be the BUS_DRERR, G, LD and MAV has been triggered in MCSR register. When I tried access CAN bus in MPC5746B. Form the triggered bits in MCSR register, is the issue related the CAN bus being "guarded" or "lock"????? Would you please confirm my logical on it? If the case, is there anyway to release this "guarded" memory area?

Thank you

James

Re: MPC5746B trapping by IVOR1_Vector

petervlna — Tue, 24 Oct 2023 07:09:04 GMT

Hello,

Have a look at MCAR for address where the failure happen.

Best regards,

Peter