Dcache as RAM in MPC5777C

Indra — Sun, 28 May 2023 09:52:55 GMT

Hi everyone, I am trying to make data cache to be used as ram in mpc5777c for that purpose I've invalidated and enable the dcache in copy back mode, then I've created a tlb entry at address 0x40040000 and set it as cacheable
The dcache code goes like this:

.section .text

.global assemblyFunction

assemblyFunction:

cfg_DCACHE:

/*--------------------------------------------#

# Invalidate - Set CINV #

# e_bit in L1CSR0 Register #

#--------------------------------------------*/

e_li r5, 0x0000

e_ori r5, r5, 0x0002

msync

isync

mtspr 1010,r5

/*-------------------------------------------#

# Mask out CINV and CAbT to see if #

# invalidation is complete (i.e. CINV=0, #

# CAbT=0) #

#-------------------------------------------*/

label_DCINV_check:

/*-------------------------------------------#

# Load Registers with Masks: #

# Load CINV mask into R8 #

# Load CAbT mask into R7 #

# Load CAbT clear mask into R11 #

#-------------------------------------------*/

e_li r8, 0x0000

e_ori r8, r8, 0x0002

e_li r7, 0x0000

e_ori r7, r7, 0x0004

e_li r11, 0xFFFF

e_or2i r11, 0xFFFB

CHECK_DCINV:

/*-------------------------------------------#

# Read 1010 register, store in r9 #

#-------------------------------------------*/

mfspr r9, 1010

/*-------------------------------------------#

# check for an Ae_bORT of the cache invalidate #

# operation #

#-------------------------------------------*/

and. r10, r7, r9

e_beq D_NO_ABORT

/*-------------------------------------------#

# If ae_bort detected, clear CAe_bT e_bit and #

# re-run invalidation #

#-------------------------------------------*/

and. r10, r11, r9

msync

isync

mtspr 1010, r10

e_b cfg_DCACHE

D_NO_ABORT:

/*-------------------------------------------#

# Check that invalidation has completed - #

# (CINV=0). branch if invalidation not #

# complete. #

#-------------------------------------------*/

and. r10, r8, r9

e_bne CHECK_DCINV

/*-------------------------------------------#

# Enable cache by performing a #

# read/modify/write of the CE bit in the #

# 1010 register #

#-------------------------------------------*/

mfspr r5, 1010

e_ori r5, r5, 0x0000

e_ori r5, r5, 0x0001 /* Store 1010 value to R5 (CE=1) */

msync

isync

mtspr 1010, r5 /* Write R5 to 1010 register */

/*-------------------------------------------#

# Enable cache by performing a #

# read/modify/write of the DCWM bit in the #

# 1010 register #

#-------------------------------------------*/

mfspr r5, 1010

e_add2is r5,0x0010 /* Store 1010 value to R5 (DCWM=1) */

msync

isync

mtspr 1010, r5 /* Write R5 to 1010 register */

e_li r3, 0x80 /* Load r3 with loop count = 4KB/32B = 128 = 0x80 */

mtCTR r3 /* Move loop count to spr CTR */

e_li r3, 0x4004 /* Point r3 to start of desired address (r3=0x40040000)*/

LockingLoop:

dcbz r0, r3 /* Establish address in cache for 32B cache line of 0's */

dcbtls 0, r0, r3 /* Lock that line in cache */

e_addi r3, r3, 0x20 /* Increment address pointer by 32 B */

e_bdnz LockingLoop

se_blr

the tlb entry is:
e_lis r3, 0x1005 /* Select TLB entry #, define R/W replacment control */
mtspr 624, r3 /* Load MAS0 with 0x1006 0000 for TLB entry #6 */
/* Define description context and configuration control:*/
/* VALID=1, IPROT=0, TID=0, TS=0, TSIZE=1 (4KB size) */
e_lis r3, 0x8000 /* Load MAS 1 with 0x8000 0100 */
e_ori r3, r3, 0x0100
mtspr 625, r3
/* Define EPN and page attributes: */
/* EPN = 0x4004 0000, WIMAGE = all 0's */
e_lis r3, 0x4004 /* Load MAS2 with 0x4004 0000 */
mtspr 626, r3
/* Define RPN and access control for data R/W */
/* RPN = 0x4004 0000, U0:3=0, UX/SX=0, UR/SR/UW/SW=1 */
e_lis r3, 0x4004 /* Load MAS3 with 0x4004 000F */
e_ori r3, r3, 0x003F
mtspr 627, r3
tlbwe

After doing all this I dont see any difference though when writing at memory address 0x40040000 nothing happens even after removing the tlb I dont see any change.
I've changed the memory to 0x40040000 just for checking the data is written on the ram but not in the dcache (I am using trace32 as debugger) the dcache shows nothing but 0 as defined in the dcache code.

BR,

Indra

Re: Dcache as RAM in MPC5777C

davidtosenovjan — Mon, 29 May 2023 14:20:34 GMT

I am not sure what you are trying to do, but this is usually done by startup code, as this area is used for core stack (as this derivative does not have TCM memories).

Re: Dcache as RAM in MPC5777C

Indra — Mon, 29 May 2023 15:52:01 GMT

Sorry foe the confusion what I want to achieve is to use dcache as ram to increase the available ram size. i referred a cookbook it says to use cache as ram the cache is invalidated and enabled in copyback mode. All I want is to increase my ram size my using dcache 16kb memory as ram is that possible

Re: Dcache as RAM in MPC5777C

davidtosenovjan — Tue, 30 May 2023 08:56:17 GMT

I see. You can use the rest of cache for increasing SRAM capability for instance as TLB6 or increase the area used for stack to 16k. A procedure described in cookbook in correct in principle.

Re: Dcache as RAM in MPC5777C

Indra — Wed, 31 May 2023 13:02:30 GMT

Hi @davidtosenovjan I've implemented everything as per the cookbook i.e. 1. making a tlb entry 2. Invalidating and enabling the cache in copyback mode 3. loacking the cache line
after this I've tried to write at the memory location but here the data is written to both cache and the main memory. Correct me if I did something wrong
BR,
Indra

Re: Dcache as RAM in MPC5777C

davidtosenovjan — Wed, 31 May 2023 14:43:55 GMT

The problem is that in the cookbook, used virtual and physical address is 0x4004_0000 but on MPC5777C there is SRAM space on that address.

Cookbook used MPC55xx and there is nothing in the memory map for that area. That's the point.

You need to choose different address, but how I already answered on address 0x4008_0000, SW startup may configure stack located in cache as we are doing it this way on MPC5777C device.

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