MPC5xxxのトピックRe: EBI interface propagation delay

EBI interface propagation delay

wittkop — Mon, 01 Feb 2016 19:51:48 GMT

I am looking at the timing of EBI interface. Does the tCOH time listed in MPC5675 datasheet table 76 include the DRAM pad delays listed in Table 47. DRAM pads AC electrical specifications?

Rephrasing the question - Do the values listed in table 76 EBI timing refer to the output pins of the device or internal nodes?

Re: EBI interface propagation delay

davidtosenovjan — Mon, 22 Feb 2016 11:48:50 GMT

I have obtained an answer from factory engineer, quoting:

“Since EBI is only present on DDR pads, those delays are already taken care of in table 76. They just need to use the right configuration of those pads.”

Re: EBI interface propagation delay

wittkop — Mon, 22 Feb 2016 20:42:03 GMT

Thank you for your reply. Can you expand on your comment, "They just need to use the right configuration of those pads"?

What is the load capacitance load for the timing parameters in table 76? Table 76 does not reference what load conditions the timing is guaranteed.

I also have a question about I/O signal TEA. I do not see a setup/hold time to D_CLKOUT in table 76. Can this be considered an asynchronous signal.

Re: EBI interface propagation delay

davidtosenovjan — Tue, 23 Feb 2016 11:38:00 GMT

TEA signal is the same group as other EBI control signals, thus specs 5,6,7 and 8 are valid for it as well. It is not asynchronous signal. I will report it as a doc bug.

Regarding “right configuration” I think it was though that pin multiplexing needs to be set proper way and thus you are moving from DDR specs to EBI specs.

However it is true that spec is missing information about loading capacitance and used slew rate. Voltage and temperature is not mentioned as well, however here we could suppose the whole temperature and voltage range. I will ask for clarification, letting you know then.

Re: EBI interface propagation delay

wittkop — Fri, 25 Mar 2016 20:31:32 GMT

Has an answer been found concerning the capacitance load which the timing parameters in table 76 are guaranteed to meet?

Re: EBI interface propagation delay

davidtosenovjan — Tue, 29 Mar 2016 07:36:16 GMT

Yes, actually I have obtained answer during Easter holiday -

“The EBI parameters were measured under following conditions:

External output load = 25pf

VDD_HV_DRAMx = 3.3V

VDD_HV_DRAM_VTTx = GND

VDD_HV_DRAM_VREF = VDD_HV_DRAMx/2

slew rate of the pins = 1ns - fastest one (Slew rate selection = 0x7)”

I am apologizing for the delay.