<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>MPC5xxx中的主题 Re: IVOR 1  Error</title>
    <link>https://community.nxp.com/t5/MPC5xxx/IVOR-13-TLB-Error/m-p/1501022#M21773</link>
    <description>&lt;P&gt;Hi Lukas,&lt;/P&gt;&lt;P&gt;I ported the code to S32DS .I checked the registers which you told me but when optimization is OFF, IVOR1_Exception_Handler function could not return to epilog_IVOR1. At the first instruction of IVOR1_Exception_Handler, we saw that lr showing the address of epilog_IVOR1.&lt;BR /&gt;At the last instruction of IVOR1_Exception_Handler, we saw that lr showing the wrong address.&lt;/P&gt;</description>
    <pubDate>Thu, 04 Aug 2022 10:03:43 GMT</pubDate>
    <dc:creator>elifceliker</dc:creator>
    <dc:date>2022-08-04T10:03:43Z</dc:date>
    <item>
      <title>IVOR 13 TLB Error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/IVOR-13-TLB-Error/m-p/1498630#M21708</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I used to below code for generating 2-bit ECC error in RAM however&amp;nbsp;generate1bitECCError() runs correctly but&amp;nbsp;generateNoncorrectableECC_error () returns IVOR13 TLB error. I also tried to&amp;nbsp;&lt;A href="https://community.nxp.com/t5/MPC5xxx/What-is-reason-behind-Data-TLB-error-IVOR13-please-help-me/m-p/554999" target="_blank"&gt;What is reason behind Data TLB error(IVOR13)? plea... - NXP Community&lt;/A&gt;&amp;nbsp;but I&amp;nbsp;didnt&amp;nbsp; check the MMU table because I didnt find it where it is.Any help will be appreciate,thanks a lot.&lt;/P&gt;</description>
      <pubDate>Mon, 01 Aug 2022 08:21:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/IVOR-13-TLB-Error/m-p/1498630#M21708</guid>
      <dc:creator>elifceliker</dc:creator>
      <dc:date>2022-08-01T08:21:10Z</dc:date>
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    <item>
      <title>Re: IVOR 13 TLB Error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/IVOR-13-TLB-Error/m-p/1499960#M21751</link>
      <description>&lt;P&gt;Hi Elif,&lt;/P&gt;
&lt;P&gt;did you use GHS Multi IDE or did you ported the code to S32DS? Most likely, there's a problem with your exception handler. Please check if IVPR+IVOR1 registers (base address + offset) really points to your machine check handler.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Lukas&lt;/P&gt;</description>
      <pubDate>Wed, 03 Aug 2022 04:57:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/IVOR-13-TLB-Error/m-p/1499960#M21751</guid>
      <dc:creator>lukaszadrapa</dc:creator>
      <dc:date>2022-08-03T04:57:29Z</dc:date>
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    <item>
      <title>Re: IVOR 13 TLB Error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/IVOR-13-TLB-Error/m-p/1500160#M21761</link>
      <description>&lt;P&gt;Hi Lukas,&lt;/P&gt;&lt;P&gt;I ported the code to S32DS .I checked the registers which you told me but when optimization is OFF, IVOR1_Exception_Handler function could not return to epilog_IVOR1. At the first instruction of IVOR1_Exception_Handler, we saw that lr showing the address of epilog_IVOR1.&lt;BR /&gt;At the last instruction of IVOR1_Exception_Handler, we saw that lr showing the wrong address.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;-c -fmessage-length=0 -fstrict-volatile-bitfields -mlra -msdata=eabi&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;//// main.c&lt;BR /&gt;static void generateNoncorrectableECC_error(void)&lt;BR /&gt;{&lt;BR /&gt;volatile uint32_t test_read = 0;&lt;/P&gt;&lt;P&gt;/* invert 2 LSB bits to create non-correctable data error */&lt;BR /&gt;EIM-&amp;gt;EICHDn[0].WORD1 = 0x00000003;&lt;BR /&gt;/* PRAMC_0 channel error injection enable */&lt;BR /&gt;EIM-&amp;gt;EICHEN = 0x80000000;&lt;BR /&gt;/* global error injection enable */&lt;BR /&gt;EIM-&amp;gt;EIMCR = 1;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;/* error caused by read (it should set MCSR[MAV, LD, BUS_DRERR]) */&lt;BR /&gt;//test_read = test[0];&lt;BR /&gt;test_read = test[0];&lt;BR /&gt;}&lt;BR /&gt;////////&lt;/P&gt;&lt;P&gt;////// exception.c&lt;BR /&gt;void foo()&lt;BR /&gt;{&lt;BR /&gt;int x = 0;&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;void IVOR1_Exception_Handler(void){&lt;/P&gt;&lt;P&gt;foo();&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;IVOR1_Handler:&lt;BR /&gt;prolog_IVOR1:&lt;BR /&gt;e_stwu r1, -0x50(r1) # Create stack frame and store back chain&lt;BR /&gt;se_stw r0, 0x10(r1) # Store GPR0 (working register)&lt;BR /&gt;se_mflr r0&lt;BR /&gt;se_stw r0, 0x14(r1) # Store LR&lt;BR /&gt;se_mfctr r0&lt;BR /&gt;se_stw r0, 0x18(r1) # Store CTR&lt;BR /&gt;mfxer r0&lt;BR /&gt;se_stw r0, 0x1C(r1) # Store XER&lt;BR /&gt;mfcr r0&lt;BR /&gt;se_stw r0, 0x20(r1) # Store CR&lt;BR /&gt;e_bl prolog_GPRs # Store GPR3-GPR12 (stack offset 0x24-0x48)&lt;/P&gt;&lt;P&gt;mfmsr r0 # As function prologs/epilogs may contain&lt;BR /&gt;e_or2is r0, 0x0200 # SPE instruction, enable SPE, as MSR&lt;BR /&gt;mtmsr r0 # register is cleared at this point&lt;/P&gt;&lt;P&gt;e_bl IVOR1_Exception_Handler # Invoke exception handler&lt;/P&gt;&lt;P&gt;epilog_IVOR1:&lt;BR /&gt;e_bl epilog_GPRs # Restore GPR3-GPR12 (stack offset 0x24-0x48)&lt;BR /&gt;se_lwz r0, 0x20(r1)&lt;BR /&gt;mtcr r0 # Restore CR&lt;BR /&gt;se_lwz r0, 0x1c(r1)&lt;BR /&gt;mtxer r0 # Restore XER&lt;BR /&gt;se_lwz r0, 0x18(r1)&lt;BR /&gt;se_mtctr r0 # Restore CTR&lt;BR /&gt;se_lwz r0, 0x14(r1)&lt;BR /&gt;se_mtlr r0 # Restore LR&lt;BR /&gt;se_lwz r0, 0x10(r1) # Restore GPR0 (working register)&lt;BR /&gt;e_add16i r1, r1, 0x50 # Clean up stack&lt;BR /&gt;se_rfmci&lt;BR /&gt;;# End IVOR1 Exception Handler&lt;/P&gt;&lt;P&gt;I used to above code,any help will be&lt;SPAN&gt;&amp;nbsp;appreciate,thanks a lot.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Elif&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 03 Aug 2022 09:45:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/IVOR-13-TLB-Error/m-p/1500160#M21761</guid>
      <dc:creator>elifceliker</dc:creator>
      <dc:date>2022-08-03T09:45:56Z</dc:date>
    </item>
    <item>
      <title>Re: IVOR 1  Error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/IVOR-13-TLB-Error/m-p/1501022#M21773</link>
      <description>&lt;P&gt;Hi Lukas,&lt;/P&gt;&lt;P&gt;I ported the code to S32DS .I checked the registers which you told me but when optimization is OFF, IVOR1_Exception_Handler function could not return to epilog_IVOR1. At the first instruction of IVOR1_Exception_Handler, we saw that lr showing the address of epilog_IVOR1.&lt;BR /&gt;At the last instruction of IVOR1_Exception_Handler, we saw that lr showing the wrong address.&lt;/P&gt;</description>
      <pubDate>Thu, 04 Aug 2022 10:03:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/IVOR-13-TLB-Error/m-p/1501022#M21773</guid>
      <dc:creator>elifceliker</dc:creator>
      <dc:date>2022-08-04T10:03:43Z</dc:date>
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  </channel>
</rss>

