<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>MPC5xxxのトピックRe: CMU</title>
    <link>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1455402#M21147</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;You can configure modes according to your needs. Simply configure only modes you are using. If you use only DRUN, I see no point of configuring RUNx modes.&lt;/P&gt;
&lt;P&gt;I do not have example SW.&lt;/P&gt;
&lt;BLOCKQUOTE&gt;
&lt;P&gt;However, I could not verify any fault in CMU_ISR for all CMUs&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;
&lt;P&gt;And do you create clock violation? For example by disconnecting crystal from board?&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;</description>
    <pubDate>Tue, 10 May 2022 06:46:02 GMT</pubDate>
    <dc:creator>petervlna</dc:creator>
    <dc:date>2022-05-10T06:46:02Z</dc:date>
    <item>
      <title>CMU</title>
      <link>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1449438#M21040</link>
      <description>&lt;P&gt;CLKMN1 frequency less than low reference event status.&lt;BR /&gt;This bit is set by hardware when CLKMN1 frequency becomes lower than the low-frequency reference&lt;BR /&gt;value determined by CMU_LFREFR[LFREF],&lt;FONT color="#FF0000"&gt;&lt;STRONG&gt; and CLKMN1 is 'ON' as signaled by the MC_ME.&lt;/STRONG&gt;&lt;/FONT&gt; Software&lt;BR /&gt;clears this field by writing a '1'.&lt;BR /&gt;0 No FLL event&lt;BR /&gt;1 FLL event occurred&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Oscillator frequency less than fCLKMT0_RMN ÷ 2CMU_CSR[RCDIV]event status.&lt;BR /&gt;This bit is set by hardware when the fCLKMN0_RMT is less than fCLKMT0_RMN ÷ 2CMU_CSR[RCDIV]frequency &lt;STRONG&gt;&lt;FONT color="#FF0000"&gt;and&lt;/FONT&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;FONT color="#FF0000"&gt;CLKMN0_RMT is 'ON' as signaled by the MC_ME&lt;/FONT&gt;&lt;/STRONG&gt;. It can be cleared by software by writing '1'.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;How shall I activate the&amp;nbsp;&lt;STRONG&gt;&lt;FONT color="#FF0000"&gt;CLKMN0_RMT is 'ON' as signaled by the MC_ME&lt;/FONT&gt;&lt;/STRONG&gt;. and&amp;nbsp;&lt;FONT color="#FF0000"&gt;&lt;STRONG&gt;CLKMN1 is 'ON' as signaled by the MC_ME. ?&lt;/STRONG&gt;&lt;/FONT&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 26 Apr 2022 23:04:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1449438#M21040</guid>
      <dc:creator>Amr_Awny</dc:creator>
      <dc:date>2022-04-26T23:04:02Z</dc:date>
    </item>
    <item>
      <title>Re: CMU</title>
      <link>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1449899#M21052</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;Yes, Otherwise you wont have CLKMN0 /1 clock active, so you wont be able to perform any measurement / monitoring.&lt;/P&gt;
&lt;P&gt;Simply enable those clocks in your target mode in Mode Entry module, for more details see the mode entry module chapter of reference manual&amp;nbsp; for your device:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="petervlna_1-1651061215081.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/178175i1B4865F7C9C184F2/image-size/medium?v=v2&amp;amp;px=400" role="button" title="petervlna_1-1651061215081.png" alt="petervlna_1-1651061215081.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="petervlna_0-1651061152752.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/178174iB7BA3E21B9A0A38B/image-size/medium?v=v2&amp;amp;px=400" role="button" title="petervlna_0-1651061152752.png" alt="petervlna_0-1651061152752.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;</description>
      <pubDate>Wed, 27 Apr 2022 12:07:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1449899#M21052</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2022-04-27T12:07:29Z</dc:date>
    </item>
    <item>
      <title>Re: CMU</title>
      <link>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1453462#M21121</link>
      <description>&lt;P&gt;Thanks for the reply,&amp;nbsp;&lt;/P&gt;&lt;P&gt;Shall I configure all the modes in or just the &lt;STRONG&gt;Drun&lt;/STRONG&gt; mode, I have checked the registers mentioned and verified if they are enabled in&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;MC_ME_GS = 0x301300f2&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;MC_ME_DRUN = 0x1300f2&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;However, I could not verify any fault in CMU_ISR for all CMUs&lt;/P&gt;&lt;P&gt;If it is possible would you share a CMU example code ?&lt;/P&gt;</description>
      <pubDate>Thu, 05 May 2022 10:43:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1453462#M21121</guid>
      <dc:creator>Amr_Awny</dc:creator>
      <dc:date>2022-05-05T10:43:05Z</dc:date>
    </item>
    <item>
      <title>Re: CMU</title>
      <link>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1455402#M21147</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;You can configure modes according to your needs. Simply configure only modes you are using. If you use only DRUN, I see no point of configuring RUNx modes.&lt;/P&gt;
&lt;P&gt;I do not have example SW.&lt;/P&gt;
&lt;BLOCKQUOTE&gt;
&lt;P&gt;However, I could not verify any fault in CMU_ISR for all CMUs&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;
&lt;P&gt;And do you create clock violation? For example by disconnecting crystal from board?&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;</description>
      <pubDate>Tue, 10 May 2022 06:46:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1455402#M21147</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2022-05-10T06:46:02Z</dc:date>
    </item>
    <item>
      <title>Re: CMU</title>
      <link>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1456555#M21155</link>
      <description>&lt;P&gt;I didn't try to disconnect the crystal on the board yet&lt;/P&gt;</description>
      <pubDate>Wed, 11 May 2022 15:53:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/CMU/m-p/1456555#M21155</guid>
      <dc:creator>Amr_Awny</dc:creator>
      <dc:date>2022-05-11T15:53:22Z</dc:date>
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  </channel>
</rss>

