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    <title>topic Re: MPC5746 Internal TVS current level in MPC5xxx</title>
    <link>https://community.nxp.com/t5/MPC5xxx/MPC5746-Internal-TVS-current-level/m-p/1451696#M21095</link>
    <description>&lt;P&gt;Hi Rhea,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Do you mean that 1uF capacitor is the only one at VDD_LV? The specification says that minumum capacitance is 4.7uF:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lukaszadrapa_0-1651474177761.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/178525i19D7973C2D05CBAA/image-size/medium?v=v2&amp;amp;px=400" role="button" title="lukaszadrapa_0-1651474177761.png" alt="lukaszadrapa_0-1651474177761.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;And it’s minimal value. It should be validated by user for given application.&lt;/P&gt;
&lt;P&gt;It is also recommended to use Progressive Clock Switching feature to avoid current spikes. Search for „Progressive Clock Switching“ in the reference manual for details.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Lukas&lt;/P&gt;</description>
    <pubDate>Mon, 02 May 2022 06:49:59 GMT</pubDate>
    <dc:creator>lukaszadrapa</dc:creator>
    <dc:date>2022-05-02T06:49:59Z</dc:date>
    <item>
      <title>MPC5746 Internal TVS current level</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5746-Internal-TVS-current-level/m-p/1450630#M21063</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;SPAN class=""&gt;&lt;SPAN&gt;I am using SPC5746R chip to design the minimum system with 1.25V using the following same circuit. During the debugging process, I found that 5746 would not work if I did not add Clv 1uF buffer capacitor to write the program with 200M main frequency. Specifically, I was stuck in the clock initialization and could not pass.&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN&gt; What mechanism triggers the microcontroller to cause this?&amp;nbsp; Thanks!&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 28 Apr 2022 10:17:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5746-Internal-TVS-current-level/m-p/1450630#M21063</guid>
      <dc:creator>RheaGao</dc:creator>
      <dc:date>2022-04-28T10:17:13Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5746 Internal TVS current level</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5746-Internal-TVS-current-level/m-p/1451696#M21095</link>
      <description>&lt;P&gt;Hi Rhea,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Do you mean that 1uF capacitor is the only one at VDD_LV? The specification says that minumum capacitance is 4.7uF:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lukaszadrapa_0-1651474177761.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/178525i19D7973C2D05CBAA/image-size/medium?v=v2&amp;amp;px=400" role="button" title="lukaszadrapa_0-1651474177761.png" alt="lukaszadrapa_0-1651474177761.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;And it’s minimal value. It should be validated by user for given application.&lt;/P&gt;
&lt;P&gt;It is also recommended to use Progressive Clock Switching feature to avoid current spikes. Search for „Progressive Clock Switching“ in the reference manual for details.&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Lukas&lt;/P&gt;</description>
      <pubDate>Mon, 02 May 2022 06:49:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5746-Internal-TVS-current-level/m-p/1451696#M21095</guid>
      <dc:creator>lukaszadrapa</dc:creator>
      <dc:date>2022-05-02T06:49:59Z</dc:date>
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