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    <title>MPC5xxxのトピックRe: S32R274 updates a specific variable in the data cache</title>
    <link>https://community.nxp.com/t5/MPC5xxx/S32R274-updates-a-specific-variable-in-the-data-cache/m-p/1447884#M21022</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;The procedure to enable cache memory can be found in AN12553, section 7.5.6 Enable cache:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/application-note/AN12553.pdf" target="_blank"&gt;https://www.nxp.com/docs/en/application-note/AN12553.pdf&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;And also in startup files of a project created by S32 Design Studio IDE:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lukaszadrapa_0-1650635790924.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177751iD9F8A4C12C1E4981/image-size/medium?v=v2&amp;amp;px=400" role="button" title="lukaszadrapa_0-1650635790924.png" alt="lukaszadrapa_0-1650635790924.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;You can use SMPU module to define which areas will be cacheable and which will be cache inhibited. There’s CI bit in SMPU_RGDn_WORD3 register.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lukaszadrapa_1-1650635838867.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177752i98E660C36E523D91/image-size/medium?v=v2&amp;amp;px=400" role="button" title="lukaszadrapa_1-1650635838867.png" alt="lukaszadrapa_1-1650635838867.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;If you use SDK, it can be configured here:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lukaszadrapa_2-1650635847604.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177753i80D96621EB4D0651/image-size/medium?v=v2&amp;amp;px=400" role="button" title="lukaszadrapa_2-1650635847604.png" alt="lukaszadrapa_2-1650635847604.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;An example of SMPU configuration without SDK can be found here (for different MCU):&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5748G-SMPU-initialization-Process-ID-test-GHS614/ta-p/1104607" target="_blank"&gt;https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5748G-SMPU-initialization-Process-ID-test-GHS614/ta-p/1104607&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Lukas&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 22 Apr 2022 13:58:09 GMT</pubDate>
    <dc:creator>lukaszadrapa</dc:creator>
    <dc:date>2022-04-22T13:58:09Z</dc:date>
    <item>
      <title>S32R274 updates a specific variable in the data cache</title>
      <link>https://community.nxp.com/t5/MPC5xxx/S32R274-updates-a-specific-variable-in-the-data-cache/m-p/1447675#M21014</link>
      <description>&lt;P&gt;Hello,&amp;nbsp;I have some chip S32R274 data cache issues.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The first is to enable the cache function. Is it possible to enable the data caching function of the relevant kernel by setting DCINV directly after setting DCE of L1CSR0?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The second issue is whether the specified variables can be set to use caching instead of all variables being cached once enabled?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;In addition, the description of cache function in the reference manual is not clear enough. I need more information about the data cache of this chip. Could you share it?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Looking forward to your reply!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 22 Apr 2022 07:13:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/S32R274-updates-a-specific-variable-in-the-data-cache/m-p/1447675#M21014</guid>
      <dc:creator>dong06</dc:creator>
      <dc:date>2022-04-22T07:13:06Z</dc:date>
    </item>
    <item>
      <title>Re: S32R274 updates a specific variable in the data cache</title>
      <link>https://community.nxp.com/t5/MPC5xxx/S32R274-updates-a-specific-variable-in-the-data-cache/m-p/1447884#M21022</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;The procedure to enable cache memory can be found in AN12553, section 7.5.6 Enable cache:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/application-note/AN12553.pdf" target="_blank"&gt;https://www.nxp.com/docs/en/application-note/AN12553.pdf&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;And also in startup files of a project created by S32 Design Studio IDE:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lukaszadrapa_0-1650635790924.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177751iD9F8A4C12C1E4981/image-size/medium?v=v2&amp;amp;px=400" role="button" title="lukaszadrapa_0-1650635790924.png" alt="lukaszadrapa_0-1650635790924.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;You can use SMPU module to define which areas will be cacheable and which will be cache inhibited. There’s CI bit in SMPU_RGDn_WORD3 register.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lukaszadrapa_1-1650635838867.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177752i98E660C36E523D91/image-size/medium?v=v2&amp;amp;px=400" role="button" title="lukaszadrapa_1-1650635838867.png" alt="lukaszadrapa_1-1650635838867.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;If you use SDK, it can be configured here:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="lukaszadrapa_2-1650635847604.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177753i80D96621EB4D0651/image-size/medium?v=v2&amp;amp;px=400" role="button" title="lukaszadrapa_2-1650635847604.png" alt="lukaszadrapa_2-1650635847604.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;An example of SMPU configuration without SDK can be found here (for different MCU):&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5748G-SMPU-initialization-Process-ID-test-GHS614/ta-p/1104607" target="_blank"&gt;https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5748G-SMPU-initialization-Process-ID-test-GHS614/ta-p/1104607&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;
&lt;P&gt;Lukas&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 22 Apr 2022 13:58:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/S32R274-updates-a-specific-variable-in-the-data-cache/m-p/1447884#M21022</guid>
      <dc:creator>lukaszadrapa</dc:creator>
      <dc:date>2022-04-22T13:58:09Z</dc:date>
    </item>
    <item>
      <title>Re: S32R274 updates a specific variable in the data cache</title>
      <link>https://community.nxp.com/t5/MPC5xxx/S32R274-updates-a-specific-variable-in-the-data-cache/m-p/1448223#M21026</link>
      <description>&lt;P&gt;Let me try.&lt;/P&gt;&lt;P&gt;Thank you for your answer, Lukas!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 25 Apr 2022 02:13:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/S32R274-updates-a-specific-variable-in-the-data-cache/m-p/1448223#M21026</guid>
      <dc:creator>dong06</dc:creator>
      <dc:date>2022-04-25T02:13:05Z</dc:date>
    </item>
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