MPC5xxxのトピックRe: How to inject error to test BAM DISABLE

How to inject error to test BAM DISABLE

AdhamGad1 — Sun, 20 Mar 2022 17:23:49 GMT

Can you please guide me to inject error in the BAM.

i already set the RAE BIT in SSCM ERROR REG.

Thanks in advanced

Re: How to inject error to test BAM DISABLE

davidtosenovjan — Wed, 23 Mar 2022 07:53:19 GMT

Also, please clarify used device.

Re: How to inject error to test BAM DISABLE

AdhamGad1 — Wed, 23 Mar 2022 09:43:29 GMT

MPC5744P

Re: How to inject error to test BAM DISABLE

davidtosenovjan — Wed, 23 Mar 2022 13:22:32 GMT

Let me check - do you want to generate access error according access rights defined in PBRIDGE registers? Just guessing what you want to do..

Re: How to inject error to test BAM DISABLE

AdhamGad1 — Wed, 23 Mar 2022 15:06:39 GMT

Yes i just want to inject error to ensure the behavior is correct

Re: How to inject error to test BAM DISABLE

AdhamGad1 — Wed, 23 Mar 2022 15:07:40 GMT

Re: How to inject error to test BAM DISABLE

davidtosenovjan — Thu, 24 Mar 2022 10:12:32 GMT

RM, section 2.4.5, described PACR/OPACR registers, what tells you which register is related to BAM.

Clearing of PBRIDGE_x_MPCR[MPLn] sets force “user mode” for particular master (this can be used for injecting of deny accesss by frocing of user mode).
Setting of PBRIDGE_x_MPCR[MPLn] means supervisor/user mode according to particular master’s setting.

If AIPS_x_PACRn[SPn] or AIPS_x_OPACRn[SPn] is set it means slave requires supervisor mode for accessing master and this can be achieved by AIPS_x_MPCR[MPLn] = 1 (+MSR[PR] = 0 in case this master is core).

If AIPS_x_PACRn[SPn] or AIPS_x_OPACRn[SPn] is cleared it means slave does not require supervisor mode for accessing master and thus AIPS_MPRA[MPLn] may be 0 (or MSR[PR] may be 1 in case this master is core).

After proper settings of that, setting of RAE bit enable exception response. Subsequently, access to affected area invoke access error.