topic Re: Disable Dcache of 5744 will make CCP unsteadiness in MPC5xxx

Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Thu, 07 Jan 2016 12:17:14 GMT

When I use the EEPROM emulation code, I need disable the dcache of 5744, or the swapping will fail.

The function of disabling dcache see below:

void dcache_disable(void)

{ /* Body */

E200CORE_SPR_GET(val,E200CORE_L1CSR0); /* L1CSR0 */

val &= ~E200CORE_L1CSR0_CE;

/* Memory Synchronize */

E200CORE_SYNC();

/* Instruction Synchronize */

E200CORE_ISYNC();

E200CORE_SPR_SET(E200CORE_L1CSR0,val);

/* Instruction Synchronize */

E200CORE_ISYNC();

} /* Endbody */

In this case,the EEPROM emulation works very well, but the CCP with VECTOR'S APE became be unsteadiness.

I want to know how to solve the contradiction between EEPROM emulation and CCP?

Re: Disable Dcache of 5744 will make CCP unsteadiness

lukaszadrapa — Thu, 07 Jan 2016 13:47:43 GMT

Hi,

as mentioned in EEE user manual, "It is highly recommended that the D-cache of core should be disable at the initialization code

to make sure the program/erase functions work properly".

I can see two options to make it bulletproof:

1. Keep the data cache disabled all the time.

2. If you want to keep the data cache enabled to improve the performance, configure the EEE area as cache inhibited in memory protection unit.

Regards,

Lukas

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Fri, 08 Jan 2016 01:13:35 GMT

For your two point of view, I think:

1. Keep the data cache disabled all the time will make my EEPROM emulation works well, but my CCP will still be unsteadiness;

2. The problem is that if I enable the D-cache, swapping block will fail, and I am sure that the flash controller cache has been disabled.

Can the D-cache make the CPU reads and writes RAM unsteadily? If I did not disable the D-cache, my CCP works very well. But swap failed.

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Fri, 08 Jan 2016 02:24:45 GMT

HI,

I noted that you used a words of " cache inhibited in memory protection unit" but not "disable flash controller cache". what is the difference of them?

I disable the " flash controller cache" by using these codes:

void DisableFlashControllerCache(UINT32 *origin_pflash_pfcr1,
                                 UINT32 *origin_pflash_pfcr2)
{
    /* Read the values of two registers FLASH_PFCR1 and FLASH_PFCR2 */
    *origin_pflash_pfcr1 = READ32(FLASH_FMC + FLASH_PFCR1);
    *origin_pflash_pfcr2 = READ32(FLASH_FMC + FLASH_PFCR2);

    /* Disable Caches */
    CLEAR32(FLASH_FMC + FLASH_PFCR1, FLASH_FMC_P0BFEN);
    CLEAR32(FLASH_FMC + FLASH_PFCR2, FLASH_FMC_P1BFEN);
}

I did not know if it is the code of " cache inhibited in memory protection unit".

If it is not, can you help me coding some instruction to " cache inhibited in memory protection unit"?

Thank you very much!

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Fri, 08 Jan 2016 07:09:50 GMT

Thank you very much!

I think I have resolved this problem by your second point of view.

I inited the SMPU and found the EEPROM emulation need not disable D-chache while swapping works very well.

Only thing should be noted is the SMPU must cover all the memory addresses could be accessed by your software project.

Thanks very much again!

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Fri, 08 Jan 2016 07:11:56 GMT

Thank you very much!

I think I have resolved this problem by your second point of view.

I inited the SMPU and found the EEPROM emulation need not disable D-chache while swapping works very well.

Only thing should be noted is the SMPU must cover all the memory addresses could be accessed by your software project.

Thanks very much again!

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Fri, 08 Jan 2016 07:14:11 GMT

In the initial of SMPU, I make the area of EEPROM "cache inhibited". This is the key operation.

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Mon, 11 Jan 2016 04:24:53 GMT

I am afraid that I did not get the root course of my problem. Because the CCP unsteadiness occurs again after I set the EEPROM enulation area "cache inhibit".

And I found that the function "FSL_InitEeprom" coursed this problem. But I don't know the reason.

Re: Disable Dcache of 5744 will make CCP unsteadiness

lukaszadrapa — Mon, 11 Jan 2016 06:47:18 GMT

Have you invalidated the data cache after SMPU initialization? If the data cache was initialized before initialization of SMPU, there could be some data already cached.

Regards,

Lukas

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Mon, 11 Jan 2016 07:23:28 GMT

Hi,

I am sure that I did not operate the D-cache at all.

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Mon, 11 Jan 2016 07:25:33 GMT

So the D-cache is enabled.

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Mon, 11 Jan 2016 08:28:02 GMT

I think I found the root course of my problem.

I masked the funciton of "DisableFlashControllerCache" in my project, and glad to see that my CCP function works very steadily.

But I do not know why the cache of flash controller will effect the CCP? we know the CCP is only operation the ram and read code of flash.

Re: Disable Dcache of 5744 will make CCP unsteadiness

lukaszadrapa — Mon, 11 Jan 2016 09:10:53 GMT

There's one more note in the user manual for EEE that explains the behavior:

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Mon, 11 Jan 2016 09:38:42 GMT

I am sure that I only operate the falsh controller cache once at the beginning of my application.

Re: Disable Dcache of 5744 will make CCP unsteadiness

lukaszadrapa — Mon, 11 Jan 2016 13:56:58 GMT

Now I'm not sure if I can understand. Is the flash buffer (mini-cache) enabled or not?

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Tue, 12 Jan 2016 05:26:28 GMT

You can see below code:

    /* Disable Caches */
    CLEAR32(FLASH_FMC + FLASH_PFCR1, FLASH_FMC_P0BFEN);
    CLEAR32(FLASH_FMC + FLASH_PFCR2, FLASH_FMC_P1BFEN);
}

If this function is operated at the beginning of my project, the CCP(CAN Calibration Protocol) works unsteadily.

Or the CCP works well.

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Wed, 13 Jan 2016 05:26:04 GMT

Do you know why I operate the function "DisableFlashControllerCache" will make the CCP unsteadily?

Re: Disable Dcache of 5744 will make CCP unsteadiness

lukaszadrapa — Wed, 13 Jan 2016 13:18:22 GMT

It doesn't make sense to me. The disabling of mini-cache should solve all troubles but it looks like it works in opposite way in your project. Could you double check in your debugger that P0BFEN and P1BFEN are cleared all the time? Is there anything what could change this setting?

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Thu, 14 Jan 2016 01:35:58 GMT

Thank you for your response. I cheked the P0BFEN and P1BFEN, they are always cleared in my project. There are no other code may change this setting.

Note: I set the EEPROM area "cache inhibit" in the SMPU. So I did not always need to "DisableFlashControllerCache".

Re: Disable Dcache of 5744 will make CCP unsteadiness

liujinhang — Mon, 18 Jan 2016 00:52:08 GMT

Hi,

can you give me some suggestion to get the root course?