https://community.nxp.com/t5/MPC5xxx/MPC5777C-IPC-shared-memory/m-p/1387925#M19904 <P>Hi,</P> <P>there's no such chapter. Both cores have an access to whole memory map, so you can use any part of RAM memory as shared memory. I can only recommend to configure this shared memory as cache inhibited - this can be done using MMU. And to ensure data coherency, you can use semaphores (SEMA4 module).</P> <P>Regards,</P> <P>Lukas</P> <P>&nbsp;</P> Thu, 16 Dec 2021 07:38:37 GMT lukaszadrapa 2021-12-16T07:38:37Z https://community.nxp.com/t5/MPC5xxx/MPC5777C-IPC-shared-memory/m-p/1386437#M19890 <P>What are the chapters in MPC5777C describe about data sharing between two Core processors ?</P> Tue, 14 Dec 2021 12:35:23 GMT https://community.nxp.com/t5/MPC5xxx/MPC5777C-IPC-shared-memory/m-p/1386437#M19890 San_96 2021-12-14T12:35:23Z https://community.nxp.com/t5/MPC5xxx/MPC5777C-IPC-shared-memory/m-p/1387925#M19904 <P>Hi,</P> <P>there's no such chapter. Both cores have an access to whole memory map, so you can use any part of RAM memory as shared memory. I can only recommend to configure this shared memory as cache inhibited - this can be done using MMU. And to ensure data coherency, you can use semaphores (SEMA4 module).</P> <P>Regards,</P> <P>Lukas</P> <P>&nbsp;</P> Thu, 16 Dec 2021 07:38:37 GMT https://community.nxp.com/t5/MPC5xxx/MPC5777C-IPC-shared-memory/m-p/1387925#M19904 lukaszadrapa 2021-12-16T07:38:37Z