MPC5xxxのトピックRe: MPC5745R's internal overlay RAM cannot be written

MPC5745R's internal overlay RAM cannot be written

冠军蔡 — Thu, 07 May 2020 03:22:15 GMT

Hi，

When i use MPC5745R ,the internal overlay RAM cannot be written.

#include "derivative.h" /* include peripheral declarations */
#include "Clock.h"
#include "PFLASH.h"
#include "SIUL2.h"

/*******************************************************************************
* Constants and macros
*******************************************************************************/
const uint32_t __attribute__ ((section(".const1"))) TEST1 = 0xFEEDFACE;
/* Will be placed to address 0x0104_0000 */

const uint32_t __attribute__ ((section(".const2"))) TEST2 = 0xCAFEBEEF;
/* Will be placed to address 0x0108_0000 */

extern void xcptn_xmpl(void);

uint32 test1;
uint32 test2;

void Overlay(uint32_t word0, uint32_t word1, uint32_t word2, uint32_t descriptor)
{
PFLASH.PFCRD[descriptor].Word0.R = word0; /* Logical address */
PFLASH.PFCRD[descriptor].Word1.R = word1; /* Physical address */
PFLASH.PFCRD[descriptor].Word2.R = word2; /* Enable remapping for individual masters, size of page */
PFLASH.PFCRDE.R |= (uint32_t)0x80000000 >> descriptor; /* Enable descriptor */
PFLASH.PFCRCR.B.GRMEN = 1; /* Global Remap Enable */
}

int main(void)
{
volatile int counter = 0;
uint32 a;
xcptn_xmpl (); /* Configure and Enable Interrupts */

Sysclk_Init();
InitPeriClkGen();

/* MPC5745R
* Internal Overlay RAM
* Start Address 0x0D000000
* End Address 0x0D003FFF
* Block size 16k
*
* */

Overlay(0x09080000, 0x0D000000, 0xFFFF0007, 0);
/* Write some values to SRAM to see the effect in flash mirrored address space */
*(uint32_t*)0x0D000000 = 0xAABBCCDD;

for(;;) {
counter++;
a++;
}
}

/**********************************************************************************************/

*(uint32_t*)0x0D000000 = 0xAABBCCDD;

The program cannot be executed。

Why?

Re: MPC5745R's internal overlay RAM cannot be written

lukaszadrapa — Tue, 12 May 2020 12:14:44 GMT

Hi,

the configuration is correct. After execution, you should see content of RAM at address 0x09080000.

The problem seems to be ECC. The overlay RAM is covered by ECC, so the RAM must be initialized. But this is not done by default in a project created in S32 Design Studio. Search for file startup.s in your project. You should see this initialization of SRAM, DMEM and IMEM:

;#***************************** Initialise SRAM ECC ***************************/
;# Store number of 128Byte (32GPRs) segments in Counter
e_lis       r5, __SRAM_SIZE@h # Initialize r5 to size of SRAM (Bytes)
e_or2i      r5, __SRAM_SIZE@l
e_srwi      r5, r5, 0x7         # Divide SRAM size by 128
mtctr       r5                  # Move to counter for use with "bdnz"

;# Base Address of the internal SRAM
e_lis r5, __SRAM_BASE_ADDR@h
e_or2i r5, __SRAM_BASE_ADDR@l

;# Fill SRAM with writes of 32GPRs
sram_loop:
    e_stmw      r0,0(r5)            # Write all 32 registers to SRAM
    e_addi      r5,r5,128           # Increment the RAM pointer to next 128bytes
    e_bdnz      sram_loop           # Loop for all of SRAM

;#************************ Initialise Local Data SRAM ECC *********************/
;# Store number of 128Byte (32GPRs) segments in Counter
e_lis       r5, __LOCAL_DMEM_SIZE@h # Initialize r5 to size of SRAM (Bytes)
e_or2i      r5, __LOCAL_DMEM_SIZE@l
e_srwi      r5, r5, 0x7         # Divide SRAM size by 128
mtctr       r5                  # Move to counter for use with "bdnz"

;# Base Address of the Local SRAM
e_lis r5, __LOCAL_DMEM_BASE_ADDR@h
e_or2i r5, __LOCAL_DMEM_BASE_ADDR@l

;# Fill Local SRAM with writes of 32GPRs
ldmem_loop:
    e_stmw      r0,0(r5)            # Write all 32 registers to SRAM
    e_addi      r5,r5,128           # Increment the RAM pointer to next 128bytes
    e_bdnz      ldmem_loop          # Loop for all of SRAM

;#************************ Initialise Local Instruction SRAM ECC **************/
;# Store number of 128Byte (32GPRs) segments in Counter
e_lis       r5, __LOCAL_IMEM_SIZE@h # Initialize r5 to size of SRAM (Bytes)
e_or2i      r5, __LOCAL_IMEM_SIZE@l
e_srwi      r5, r5, 0x7         # Divide SRAM size by 128
mtctr       r5                  # Move to counter for use with "bdnz"

;# Base Address of the Local SRAM
e_lis r5, __LOCAL_IMEM_BASE_ADDR@h
e_or2i r5, __LOCAL_IMEM_BASE_ADDR@l

;# Fill Local SRAM with writes of 32GPRs
limem_loop:
    e_stmw      r0,0(r5)            # Write all 32 registers to SRAM
    e_addi      r5,r5,128           # Increment the RAM pointer to next 128bytes
    e_bdnz      limem_loop          # Loop for all of SRAM

You need to initialize overlay RAM in the same way. You can add the initialization below this code. Just change the base address and size.

If the initialization is not done, you are accessing double words corrupted by double bit ECC error, so Machine Check exception is triggered. This should solve the problem.

Regards,

Lukas

Re: MPC5745R's internal overlay RAM cannot be written

SivaValeo — Thu, 18 Nov 2021 08:30:34 GMT

Hello Lukas,

I have tried with SRAM initialization, but written code not reflected in Mirror memory.

Flash Mirror location => 0x08FF0000; (Logical address)

RAM location => 0x40010000; (Physical address)

PFLASH_PFCRD0_Word0 = 0x08FF000;
PFLASH_PFCRD0_Word1 = 0x4001000;
PFLASH_PFCRD0_Word2 = 0xFFFF0005;
PFLASH_PFCRCR |= 0x00000001;
PFLASH_PFCRDE |= 0x80000000;

/*Also added SRAM initialization code*/

#pragma asm

//;#************************ Initialise Local Data SRAM ECC *********************/
//;# Store number of 128Byte (32GPRs) segments in Counter
e_lis r5, __SRAM_SIZE_DEBUG@h //# Initialize r5 to size of SRAM (Bytes)
e_or2i r5, __SRAM_SIZE_DEBUG@l
e_srwi r5, r5, 0x7 //# Divide SRAM size by 128
mtctr r5 //# Move to counter for use with "bdnz"

//;# Base Address of the Local SRAM
e_lis r5, __SRAM_BASE_ADDR_DEBUG@h
e_or2i r5, __SRAM_BASE_ADDR_DEBUG@l

//;# Fill Local SRAM with writes of 32GPRs
ldmem_loop:
e_stmw r0,0(r5) //# Write all 32 registers to SRAM
e_addi r5,r5,128 //# Increment the RAM pointer to next 128bytes
e_bdnz ldmem_loop //# Loop for all of SRAM

#pragma endasm

dst8 = 0x40010008;
*dst8 = 200;

if i write in SRAM, it is not reflecting in Mirror memory

is anything i have missed ?

Re: MPC5745R's internal overlay RAM cannot be written

SivaValeo — Thu, 18 Nov 2021 08:32:04 GMT

Also i am using MPC5744P