topic Machine Check Exception occur with data cache enabled on MPC5746C multi-core project in MPC5xxx

Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

1045302770 — Thu, 28 Oct 2021 08:55:44 GMT

Dear NXP team,

I am developing a multi-core project on MPC5746C, instruction cache and data cache of Z4 core is enabled at startup. To avoid cache coherency problem, SMPU is enabled and a region in system RAM is set as cache inhibited for inter-core communication. A machine check exception occurs with MAV/LD/BUS_RDERR set in MCSR, the example code of Z4 core and Z2 core are as follows:

/************************************

* Z4 core Code

***********************************/

#pragma ghs section data = ".NONE_CACHE_RAM" /*NONE_CACHE_RAM refers the cache inhibited region of SMPU*/

unsigned int z4_write_var = 1;

#pragma ghs section data = default

void test_code_z4(void)

{

while(1)

{

z4_write_var++;

}

/************************************

* Z2 core Code

***********************************/

extern unsigned int z4_write_var;

unsigned int z2_read_var;

void test_code_z2(void)

{

while(1)

{

z2_read_var = z4_write_var;

}

The running result of the program is that a machine check exception occurs, MAV/LD/BUS_RDERR are set in MCSR, and MCAR indicates the address of z4_write_var, I have checked .map file and I’m sure that z4_write_var locates within the cache inhibit region ".NONE_CACHE_RAM". And I have checked MEMU module, there is nothing indicating an ECC or EDC error.

I want to know what is the reason for the exception , and how to deal with it.

Looking forward for a reply!

Best Regards!

Victor

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

1045302770 — Fri, 29 Oct 2021 07:51:31 GMT

@lukaszadrapa @davidtosenovjan Sorry for bothering you, but would you please give me some advice to solve this problem?

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

davidtosenovjan — Fri, 29 Oct 2021 10:16:29 GMT

Hi, in this test case i would say, possible cause be XBAR priority setting

davidtosenovjan_0-1635502497901.png

I would try to use round-robin configuration for both cores. Let me know if it helps or not

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

1045302770 — Fri, 29 Oct 2021 12:00:04 GMT

Hi, thanks for your reply.

I have tried to use round-robin configuration, but it doesn't work, the exception still happens. My original XBAR configuration is as followse:

1045302770_0-1635508780887.png

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

davidtosenovjan — Mon, 01 Nov 2021 07:12:52 GMT

Have you checked CMPU setting for second core? Isn't access restricted?

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

1045302770 — Wed, 03 Nov 2021 01:33:44 GMT

I have checked it, the word2 of the NONE_CACHE_RAM memory region is 0xF3FCF000. And the exception occurs after z4_write_var counts for a while and z2_read_var changes normally until the exception occurs.

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

davidtosenovjan — Wed, 03 Nov 2021 09:21:08 GMT

Is this error dependent on running of z4 core? If you stop z4, letting only z2 core at run, does it lead in exception as well?

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

1045302770 — Thu, 04 Nov 2021 00:48:19 GMT

If you stop z4, letting only z2 core at run, does it lead in exception as well?

No, I have tested for minutes, there is no exception.

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

1045302770 — Thu, 04 Nov 2021 01:23:57 GMT

Some additional information, when data cache is disabled or smpu is disabled, no exception occurs.

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

davidtosenovjan — Thu, 04 Nov 2021 08:22:48 GMT

It should not be any difference between disabled cache and access to the SMPU region with cache inhibited attribute. Please check SMPU setting. Btw it is stated that aborted core accesses generate instruction storage (ISI) or data storage (DSI) interrupts, what would fit to described behavior.

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

1045302770 — Mon, 15 Nov 2021 01:24:11 GMT

Sorry, I was on vacation these days. I have checked SMPU setting, there is no overlapping between SMPU regions, and the setting of the NON_CACHE_RAM is as follows:

REG_WRITE32(SMPU_0_RGD7_W2, 0xf3fcf000);
REG_WRITE32(SMPU_0_RGD7_W3, 0x00000002);
REG_WRITE32(SMPU_0_RGD7_W4, 0x00000000);
REG_WRITE32(SMPU_0_RGD7_W5, 0x00000001);

And I don't know what "aborted core accesses" is, would you please give me some special example.

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

davidtosenovjan — Mon, 15 Nov 2021 09:49:43 GMT

I mean that access can be terminated (aborted) by SMPU. You could investigate SMPU status registers at the time of error.

davidtosenovjan_0-1636969706809.png

Re: Machine Check Exception occur with data cache enabled on MPC5746C multi-core project

1045302770 — Tue, 23 Nov 2021 13:16:24 GMT

The Error Status Register of SMPU did not imply any errors.

Does this problem have anything to do with the Store Buffer.

I just tried to disable the store buffer by the following code,

__MTSPR(976,0x00000008)

Then the program runs for 30 minutes with no error, I will test for longer time, I will update the test result to you tomorrow.

Thanks again for your help.