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    <title>topic Re: MPC5744, can't inject a SRAM correctable ECC error in MPC5xxx</title>
    <link>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1261274#M17962</link>
    <description>&lt;P&gt;Hi Peter,&lt;/P&gt;&lt;P&gt;By setting the dcr E2EECSR0 to 0x1001, it can generate a single ECC error for next CPU external write access, and it will be detected by MEMU for the next CPU read access.&lt;/P&gt;&lt;P&gt;My problem is I can set the dcr E2EECSR0 to 0x1001, but MEMU can't detect a SR_CE.&lt;/P&gt;&lt;P&gt;My code references the excemple:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5744P-1b-2b-RAM-ECC-error-injection-GHS714/ta-p/1117504" target="_blank"&gt;https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5744P-1b-2b-RAM-ECC-error-injection-GHS714/ta-p/1117504&lt;/A&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 13 Apr 2021 12:26:02 GMT</pubDate>
    <dc:creator>Jamber_H</dc:creator>
    <dc:date>2021-04-13T12:26:02Z</dc:date>
    <item>
      <title>MPC5744, can't inject a SRAM correctable ECC error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1260659#M17957</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I want inject a SRAM correctable ECC error by config the dcr E2EECSR0. I can set the E2EECSR0, but can't generate a SR_CE in MEMU, what's the reason about it? Does it have relation with aligment or link command file?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="2021-04-12_225824.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/142037iEDCFE086F7E97CBF/image-size/medium?v=v2&amp;amp;px=400" role="button" title="2021-04-12_225824.png" alt="2021-04-12_225824.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; Best regards&lt;/P&gt;&lt;P&gt;Jamber&lt;/P&gt;</description>
      <pubDate>Mon, 12 Apr 2021 15:14:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1260659#M17957</guid>
      <dc:creator>Jamber_H</dc:creator>
      <dc:date>2021-04-12T15:14:36Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5744, can't inject a SRAM correctable ECC error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1261258#M17961</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;I am quite confused here.&lt;/P&gt;
&lt;P&gt;It looks like you are talking bout 2 different things.&lt;/P&gt;
&lt;P&gt;1.ECC single bit error in RAM&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="petervlna_0-1618314928053.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/142129i56F6EB2D4CDC0CFC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="petervlna_0-1618314928053.png" alt="petervlna_0-1618314928053.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;2. E2E ECC protection&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="petervlna_1-1618315131771.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/142130iAB0CF4D29D2FEB21/image-size/medium?v=v2&amp;amp;px=400" role="button" title="petervlna_1-1618315131771.png" alt="petervlna_1-1618315131771.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;So which one you want to inject? ECC on RAM array?&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 13 Apr 2021 11:59:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1261258#M17961</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2021-04-13T11:59:20Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5744, can't inject a SRAM correctable ECC error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1261274#M17962</link>
      <description>&lt;P&gt;Hi Peter,&lt;/P&gt;&lt;P&gt;By setting the dcr E2EECSR0 to 0x1001, it can generate a single ECC error for next CPU external write access, and it will be detected by MEMU for the next CPU read access.&lt;/P&gt;&lt;P&gt;My problem is I can set the dcr E2EECSR0 to 0x1001, but MEMU can't detect a SR_CE.&lt;/P&gt;&lt;P&gt;My code references the excemple:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5744P-1b-2b-RAM-ECC-error-injection-GHS714/ta-p/1117504" target="_blank"&gt;https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5744P-1b-2b-RAM-ECC-error-injection-GHS714/ta-p/1117504&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 13 Apr 2021 12:26:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1261274#M17962</guid>
      <dc:creator>Jamber_H</dc:creator>
      <dc:date>2021-04-13T12:26:02Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5744, can't inject a SRAM correctable ECC error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1261628#M17967</link>
      <description>&lt;P&gt;Hi Peter,&lt;/P&gt;&lt;P&gt;What I want to do is shown in this figure. Is there some misunderstand about SR_CE injection and detection with me?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="2021-04-13_203929.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/142187iB91312CD955CC5EA/image-size/medium?v=v2&amp;amp;px=400" role="button" title="2021-04-13_203929.png" alt="2021-04-13_203929.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt; Best Regards&lt;/P&gt;&lt;P&gt;Jamber&lt;/P&gt;</description>
      <pubDate>Wed, 14 Apr 2021 02:41:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1261628#M17967</guid>
      <dc:creator>Jamber_H</dc:creator>
      <dc:date>2021-04-14T02:41:17Z</dc:date>
    </item>
    <item>
      <title>Re: MPC5744, can't inject a SRAM correctable ECC error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1263287#M18003</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;The fault will be reported in SR_CE as manual express.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="petervlna_1-1618555597651.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/142453i25864E1DF5CC1C3F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="petervlna_1-1618555597651.png" alt="petervlna_1-1618555597651.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;BLOCKQUOTE&gt;
&lt;P&gt;My problem is I can set the dcr E2EECSR0 to 0x1001, but MEMU can't detect a SR_CE.&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;
&lt;P&gt;Set the example accordingly and run it:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="petervlna_0-1618555221261.png" style="width: 488px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/142451i673C9E0E9B14D791/image-dimensions/488x345?v=v2" width="488" height="345" role="button" title="petervlna_0-1618555221261.png" alt="petervlna_0-1618555221261.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;I was just talking to the demo code author and there is not known issue with it.&lt;/P&gt;
&lt;P&gt;The fault is also reported in FCCU NCFSx register.&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Peter&lt;/P&gt;</description>
      <pubDate>Fri, 16 Apr 2021 06:52:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/MPC5744-can-t-inject-a-SRAM-correctable-ECC-error/m-p/1263287#M18003</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2021-04-16T06:52:48Z</dc:date>
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