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    <title>topic Re: 16 Bit and 32 Bit memory interface with EBI on MPC5777C in MPC5xxx</title>
    <link>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1244831#M17641</link>
    <description>&lt;P&gt;3) 0x2000AA55. Configure EBI_BR and EBI_OR registers according EBI FAQ no.5&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;4) I think we don’t have example for combined 16-bit/32-bit muxed mode.&lt;/P&gt;
&lt;P&gt;Here you may see example for 32-bit memory:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5777C-External-SRAM-test-GHS714/ta-p/1112357" target="_blank"&gt;https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5777C-External-SRAM-test-GHS714/ta-p/1112357&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;5) EBI FAQs no. 4:&lt;/P&gt;
&lt;P&gt;“EBI line with highest number (dependent on data bus width – A31 for 8bit bus, A30 16bit bus and A29 for 32bit bus) is connected to memory LSB address line, then downwards according to size of connected memory.”&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;In principle in case 32-bit data port size - ADDR(31:30) are being substituted by four byte strobe (write enable) lines.&lt;/P&gt;
&lt;P&gt;In case 16-bit data port size - ADDR(31) is being substituted by two byte strobe (write enable) lines.&lt;/P&gt;
&lt;P&gt;In case 8-bit data port size - strobe line is unnecessary as all data goes via one 8-bit port. But EBI does not support 8-bit data bus! There is no use for ADDR(31)&lt;/P&gt;</description>
    <pubDate>Fri, 12 Mar 2021 12:20:15 GMT</pubDate>
    <dc:creator>davidtosenovjan</dc:creator>
    <dc:date>2021-03-12T12:20:15Z</dc:date>
    <item>
      <title>16 Bit and 32 Bit memory interface with EBI on MPC5777C</title>
      <link>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1244367#M17627</link>
      <description>&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ashok_majeegb_0-1615492900398.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/139416i7DCD6311D7098CD2/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ashok_majeegb_0-1615492900398.png" alt="ashok_majeegb_0-1615492900398.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ashok_majeegb_1-1615492958529.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/139417i41CAFA00142985B1/image-size/medium?v=v2&amp;amp;px=400" role="button" title="ashok_majeegb_1-1615492958529.png" alt="ashok_majeegb_1-1615492958529.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 11 Mar 2021 20:03:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1244367#M17627</guid>
      <dc:creator>ashok_majeegb</dc:creator>
      <dc:date>2021-03-11T20:03:42Z</dc:date>
    </item>
    <item>
      <title>Re: 16 Bit and 32 Bit memory interface with EBI on MPC5777C</title>
      <link>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1244820#M17640</link>
      <description>&lt;P&gt;1, 2) You can use them together excluding configuration marked below:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="davidtosenovjan_1-1615549689902.png" style="width: 568px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/139493i6434D0289D1BD426/image-dimensions/568x474?v=v2" width="568" height="474" role="button" title="davidtosenovjan_1-1615549689902.png" alt="davidtosenovjan_1-1615549689902.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;You must use only multiplexed mode (pay attention to EBI FAQ no.7).&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;Set EBI_MCR[DBM] as 0 that is 32-bit port.&lt;BR /&gt;Access to 16-bit memory will have set PS = 1 that is 16-bit port.&lt;BR /&gt;Whether data goes over LSB 16-bit or MSB 16-bit is defined by EBI_MCR[D16_31]. I would recommend to use D16_31 = 1 because then you could save D_ADD pins, but it is up to you.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="davidtosenovjan_3-1615550450961.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/139497i361E7349DDFF530E/image-size/medium?v=v2&amp;amp;px=400" role="button" title="davidtosenovjan_3-1615550450961.png" alt="davidtosenovjan_3-1615550450961.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 12 Mar 2021 12:01:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1244820#M17640</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2021-03-12T12:01:08Z</dc:date>
    </item>
    <item>
      <title>Re: 16 Bit and 32 Bit memory interface with EBI on MPC5777C</title>
      <link>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1244831#M17641</link>
      <description>&lt;P&gt;3) 0x2000AA55. Configure EBI_BR and EBI_OR registers according EBI FAQ no.5&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;4) I think we don’t have example for combined 16-bit/32-bit muxed mode.&lt;/P&gt;
&lt;P&gt;Here you may see example for 32-bit memory:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5777C-External-SRAM-test-GHS714/ta-p/1112357" target="_blank"&gt;https://community.nxp.com/t5/MPC5xxx-Knowledge-Base/Example-MPC5777C-External-SRAM-test-GHS714/ta-p/1112357&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;5) EBI FAQs no. 4:&lt;/P&gt;
&lt;P&gt;“EBI line with highest number (dependent on data bus width – A31 for 8bit bus, A30 16bit bus and A29 for 32bit bus) is connected to memory LSB address line, then downwards according to size of connected memory.”&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;In principle in case 32-bit data port size - ADDR(31:30) are being substituted by four byte strobe (write enable) lines.&lt;/P&gt;
&lt;P&gt;In case 16-bit data port size - ADDR(31) is being substituted by two byte strobe (write enable) lines.&lt;/P&gt;
&lt;P&gt;In case 8-bit data port size - strobe line is unnecessary as all data goes via one 8-bit port. But EBI does not support 8-bit data bus! There is no use for ADDR(31)&lt;/P&gt;</description>
      <pubDate>Fri, 12 Mar 2021 12:20:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1244831#M17641</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2021-03-12T12:20:15Z</dc:date>
    </item>
    <item>
      <title>Re: 16 Bit and 32 Bit memory interface with EBI on MPC5777C</title>
      <link>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1244832#M17642</link>
      <description>&lt;P&gt;One yet note to you memories M3/M4. Such connection is possible and user sometimes use it, but mostly in case there are no CS line left. But in you case you have free CS2 so why you don’t use CS2 and CS3 for these two memories?&lt;/P&gt;</description>
      <pubDate>Fri, 12 Mar 2021 12:23:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1244832#M17642</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2021-03-12T12:23:50Z</dc:date>
    </item>
    <item>
      <title>Re: 16 Bit and 32 Bit memory interface with EBI on MPC5777C</title>
      <link>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1245231#M17647</link>
      <description>&lt;P&gt;Thank You David for quick response !!&amp;nbsp;&lt;/P&gt;&lt;P&gt;Now i am stage of preparing schematics of MPC 5777C interface with&lt;/P&gt;&lt;P&gt;a) 16 bit RT Memory,&lt;/P&gt;&lt;P&gt;b) 16 bit NOR flash&lt;/P&gt;&lt;P&gt;c) 16 Bit FPGA Memory&lt;/P&gt;&lt;P&gt;d) 16/32&amp;nbsp; bit burst SRAM.&amp;nbsp;&lt;/P&gt;&lt;P&gt;if i considered 16 bit SRAM , then all memory are 16bit bit , in that case&amp;nbsp;can i&amp;nbsp;&lt;SPAN&gt;Set EBI_MCR[DBM] as 1, that is 16-bit port.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;where all memory LSB address A0 need to connect&amp;nbsp;Addr 30 of MCU .&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Can you provide details EBI connection with these&amp;nbsp;memories.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;2nd query :&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;2. if Some peripheral GPIO pins and EBI pins&amp;nbsp; of MCU are connected to FPGA . is there&amp;nbsp; any&amp;nbsp; booting problem&amp;nbsp; or something issue will arrive&amp;nbsp;?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;My interest some of the eTPUs and peripheral (GPIO)&amp;nbsp; want to route to FPFA for other purpose ( not sure where to connect this moments) .&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;3rd Query :&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;3.&amp;nbsp; what is the purpose for use 32bit SRAM in MPC5777C -516DS board ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 14 Mar 2021 12:21:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/16-Bit-and-32-Bit-memory-interface-with-EBI-on-MPC5777C/m-p/1245231#M17647</guid>
      <dc:creator>ashok_majeegb</dc:creator>
      <dc:date>2021-03-14T12:21:39Z</dc:date>
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