topic Re: Exceptions involving SWT_B for MPC5777C in MPC5xxx

Exceptions involving SWT_B for MPC5777C

ikarkala — Thu, 23 Jan 2020 13:51:26 GMT

Hi,

Trying to under stand few things with respect to SWT_B for MPC5777C

1. What is a non maskable interrupt (NMI) ?

2. What is critical interrupt ?

3.What causes SWT_B to throw a non maskable interrupt (NMI) or critical interrupt ?

4. In the reference manual it says we can program SIU_DIRER to send either of the above interrupts from SWT_B.

What might cause these exceptions to come?

5. What can be done to avoid these exceptions.

Please Advice .

Thank You

Re: Exceptions involving SWT_B for MPC5777C

petervlna — Fri, 24 Jan 2020 09:26:13 GMT

Hello,

1. What is a non maskable interrupt (NMI) ?

non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore. It typically occurs to signal attention for non-recoverable hardware errors. (Some NMIs may be masked, but only by using proprietary methods specific to the particular NMI.)

2. What is critical interrupt ?

Book E–defined. Critical input, watchdog timer, and debug interrupts. these interrupts can be taken during a noncritical interrupt or during regular program flow. Book E defines the critical input, watchdog timer, debug, and machine check interrupts as critical interrupts. The EIS defines additional resources for machine check and debug interrupts.

3.What causes SWT_B to throw a non maskable interrupt (NMI) or critical interrupt ?

If your SWT_B [SWT_CR] register ITR bit is set to 1 - than on first timeout you will get interrupt (critical)

Generate an interrupt on an initial time-out; generate a reset request on a second consecutive time-out.

Refer to core reference manual.

4. In the reference manual it says we can program SIU_DIRER to send either of the above interrupts from SWT_B.
What might cause these exceptions to come?

Connected external signals (with correct levels) along with enabled DIRER in micro.

The SIU_DIRER enables external signals on selected pins to generate DMA or interrupt requests, and the SWT modules to generate interrupt requests.

5. What can be done to avoid these exceptions.

Hmm, do not enable this feature if you wont have exceptions from those sources.

regards,

Peter

Re: Exceptions involving SWT_B for MPC5777C

ikarkala — Tue, 28 Jan 2020 10:10:09 GMT

Peter,

Thank you for the quick and apt response .

Need one more clarification please .

As per the Reference Manual version 8( Figure 8-1613. NMI, critical, and SWT interrupts)

When ITR bit is set to 1 in SWT_B [SWT_CR] register an interrupt is raised for the inital time out , as per my understanding the Interrupt is routed to INTC module which triggers IRQ[501]and Critical/NMI core(based on our selection in SIUDIRER).

1.When timeout occurs both these interrupts are raised ?

2.Should both these interrupts (IIRQ[501] and Cricitcal/NMI) be serviced ?

3. If we have not configured IVOR0(Critical Input) and only IRQ[501] is serviced are there any consequences ?

Thank You

Re: Exceptions involving SWT_B for MPC5777C

petervlna — Tue, 28 Jan 2020 13:25:35 GMT

Hello,

1.When timeout occurs both these interrupts are raised ?

Both of them will be triggered at same time.

2.Should both these interrupts (IIRQ[501] and Cricitcal/NMI) be serviced ?

Service just one is enough. Depends on the masking if the external or Critical/NMI is used.

3. If we have not configured IVOR0(Critical Input) and only IRQ[501] is serviced are there any consequences ?

This is application dependent. But I would at least rise the priority on SWT interrupts.

regards,
Peter

Re: Exceptions involving SWT_B for MPC5777C

ikarkala — Mon, 03 Feb 2020 10:27:12 GMT

Peter,

Thank you so much for your valuable advice.

Appreciate it .

Regards,

Indira Karkala