topic Re: MPC5748G CAN-FD Reception in MPC5xxx

MPC5748G CAN-FD Reception

bindu_madhavan — Tue, 17 Mar 2020 13:23:07 GMT

Micontroller: MPC5748G

Peripheral: FlexCAN

Channel: CAN 0

Baudrate: CAN-FD 1000 Kbps

Hardware: DevKit

Software: attached

Question: We are trying to Transmit a message on MB-0 and do an internal loop back to receive it back on MB-1. We do not see the message being received on the MB. Not sure if we are missing anything. Can we get some help?

Re: MPC5748G CAN-FD Reception

PetrS — Wed, 18 Mar 2020 13:19:13 GMT

Hi,

the header file does not distinguish memory partitions for CAN FD and it assumes just 8byte payload.

So when you access MB[1].CS it actually writes/reads MB offset 0x90 and no the correct one 0xC8 which is CS work of MB1 if 64 payload is configured.

So address the correct memory, see Table 43-16 of the RM.

BR, Petr

Re: MPC5748G CAN-FD Reception

bindu_madhavan — Thu, 19 Mar 2020 09:21:45 GMT

Thanks Petr.

Other concern I saw was regarding RXIMR register. I had written 0x1FFFFFFF to most of the RXIMR registers and I see it getting loaded. But after clearing FRZ & HALT bits in MCR and a wait until FRZACK, they surprisingly get reassigned to its memory map address values

RXIMR[0] = 0xFFEC0880

RXIMR[1] = 0xFFEC0884

RXIMR[2] = 0xFFEC0888

RXIMR[3] = 0xFFEC088C

etc.

Any idea why?

Re: MPC5748G CAN-FD Reception

PetrS — Thu, 19 Mar 2020 11:14:40 GMT

Hi,

RXIMRs are not accessible outside Freeze mode, so maybe debugger shows address value. When you put back to Freeze mode you should see right value again.

BR, Petr