<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>MPC5xxxのトピックRe: Read SRAM occur error</title>
    <link>https://community.nxp.com/t5/MPC5xxx/Read-SRAM-occur-error/m-p/953203#M14352</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, according to the reference manual, I would say it is not possible to do it so on this device.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_11.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/85139i4CF0B85D6A8AF8FE/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_11.png" alt="pastedImage_11.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 27 Sep 2019 14:38:29 GMT</pubDate>
    <dc:creator>davidtosenovjan</dc:creator>
    <dc:date>2019-09-27T14:38:29Z</dc:date>
    <item>
      <title>Read SRAM occur error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/Read-SRAM-occur-error/m-p/953202#M14351</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hello:&lt;/P&gt;&lt;P&gt;&amp;nbsp;I&amp;nbsp;have divided a piece of SRAM in the App program(MCU: S32R274), which will be initialized once only when the power on. other reset conditions are not initialized. the purpose of this is mainly for som information interaction between bootloader and App. However, after i do this, &lt;STRONG&gt;the first function reset of the app will be ok, but when i do the second function reset, a BUS_DRERR(Read bus error on data load or linefill)&lt;/STRONG&gt; will be generated, the RGM_DES.F_EDR = 1,RGM_FES.F_ST_DONE = 1 , &lt;SPAN&gt;RGM_FES.&lt;/SPAN&gt;F_SOFT_FUNC = 1,&amp;nbsp; why is this?&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;reset command&lt;/STRONG&gt; &lt;/EM&gt;:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;MC_ME.MCTL.R = 0x00005AF0 ;&lt;BR /&gt;&amp;nbsp; &amp;nbsp;MC_ME.MCTL.R = 0x0000A50F;&lt;BR /&gt;&amp;nbsp; &amp;nbsp;while(1); // wait reset&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;&lt;STRONG&gt;the initialization code is as follow(Startup.s)&lt;/STRONG&gt; &lt;/EM&gt;:&lt;/P&gt;&lt;P&gt;;# check power on flag&lt;BR /&gt;&lt;STRONG&gt;blapcomsram_init:&lt;/STRONG&gt;&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_li r7,-360448&amp;nbsp; &amp;nbsp;&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;se_lwz r7,0(r7)&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;se_andi r7,1&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;se_extzb r7&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;se_cmpi r7,0&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_mcrf cr7&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;mfcr r7&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_rlwinm r7,r7,28,0,3&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;mtcrf 128,r7&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_beq sram_Init&amp;nbsp;;# check the&amp;nbsp;RGM.DES.B.F_POR , if == 1 , init the divided SRAM, ==0 do not init.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;;#&amp;nbsp;&lt;SPAN&gt;__SRAM_COMMON_SIZE = 128 bytes.&amp;nbsp;&amp;nbsp;__SRAM_COMMON_BASE_ADDR = 0x40000000&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;e_lis r5, __SRAM_COMMON_SIZE@h # Initialize r5 to size of SRAM (Bytes)&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_or2i r5, __SRAM_COMMON_SIZE@l&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_srwi r5, r5, 0x7 # Divide SRAM size by 128&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;mtctr r5 # Move to counter for use with "bdnz"&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;;# Base Address of the internal SRAM&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_lis r5, __SRAM_COMMON_BASE_ADDR@h&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_or2i r5, __SRAM_COMMON_BASE_ADDR@l&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;;&amp;nbsp;# Fill SRAM with writes of 32GPRs&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_li r0, 0&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_li r1, 0&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_li r2, 0&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_li r3, 0&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_li r4, 200&lt;BR /&gt;&lt;STRONG&gt;blapcomsram_loop:&lt;/STRONG&gt;&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_stmw r0,0(r5) # Write all 32 registers to SRAM&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_addi r5,r5,128 # Increment the RAM pointer to next 128bytes&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_bdnz blapcomsram_loop # Loop for all of SRAM&lt;BR /&gt;&lt;STRONG&gt;clearpwonflag:&lt;/STRONG&gt;&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;e_li r7,-360448&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;se_lwz r6,0(r7)&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;se_bseti r6,31&lt;BR /&gt; &amp;nbsp;&amp;nbsp;&amp;nbsp;se_stw r6,0(r7)&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;sram_Init:&amp;nbsp;&lt;/STRONG&gt; &amp;nbsp;&lt;/P&gt;&lt;P&gt;;# other sram init&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thank you!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Sep 2019 14:05:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/Read-SRAM-occur-error/m-p/953202#M14351</guid>
      <dc:creator>jjr_net</dc:creator>
      <dc:date>2019-09-20T14:05:42Z</dc:date>
    </item>
    <item>
      <title>Re: Read SRAM occur error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/Read-SRAM-occur-error/m-p/953203#M14352</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, according to the reference manual, I would say it is not possible to do it so on this device.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_11.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/85139i4CF0B85D6A8AF8FE/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_11.png" alt="pastedImage_11.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Sep 2019 14:38:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/Read-SRAM-occur-error/m-p/953203#M14352</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2019-09-27T14:38:29Z</dc:date>
    </item>
    <item>
      <title>Re: Read SRAM occur error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/Read-SRAM-occur-error/m-p/953204#M14353</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;thank you !!!!&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;But why is the first function reset possible?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;In addtion, I think where can the information shared between bootloader and application be stored? Are there any good Suggestions, such as how can we know whether it is the power reset,app jump or other resons for reset into bootloader?&lt;/P&gt;&lt;P&gt;&amp;nbsp; Looking forward to your help!!! thank you.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Sep 2019 15:18:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/Read-SRAM-occur-error/m-p/953204#M14353</guid>
      <dc:creator>jjr_net</dc:creator>
      <dc:date>2019-09-27T15:18:06Z</dc:date>
    </item>
    <item>
      <title>Re: Read SRAM occur error</title>
      <link>https://community.nxp.com/t5/MPC5xxx/Read-SRAM-occur-error/m-p/953205#M14354</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;HI, I have heard core register USPRG0 may be used for the purpose.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 30 Sep 2019 08:25:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/Read-SRAM-occur-error/m-p/953205#M14354</guid>
      <dc:creator>davidtosenovjan</dc:creator>
      <dc:date>2019-09-30T08:25:22Z</dc:date>
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  </channel>
</rss>

