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    <title>MPC5xxxのトピックRe: No IVOR1 exception even after ERM module reports errors</title>
    <link>https://community.nxp.com/t5/MPC5xxx/No-IVOR1-exception-even-after-ERM-module-reports-errors/m-p/931817#M13974</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;That's correct.&lt;/P&gt;&lt;P&gt;Single bit will not cause exception. As the single bit event is automatically repaired by ECC machine.&lt;/P&gt;&lt;P&gt;However multibit ECC will cause IVOR1.&lt;/P&gt;&lt;P&gt;For multibit you have to enable it in example code.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt;Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 20 Jun 2019 08:13:05 GMT</pubDate>
    <dc:creator>petervlna</dc:creator>
    <dc:date>2019-06-20T08:13:05Z</dc:date>
    <item>
      <title>No IVOR1 exception even after ERM module reports errors</title>
      <link>https://community.nxp.com/t5/MPC5xxx/No-IVOR1-exception-even-after-ERM-module-reports-errors/m-p/931814#M13971</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi ,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am trying to inject an error via EIM and detect via ERM as per example. the example is working as&amp;nbsp; expected but when in do the same thing in my code my ERM is detecting the error but is not able to invoke IVOR1 handler.&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;link to example&amp;nbsp;&lt;/SPAN&gt;&lt;A _jive_internal="true" data-containerid="11363" data-containertype="14" data-content-finding="Community" data-objectid="328097" data-objecttype="102" href="https://community.nxp.com/docs/DOC-328097" style="color: #3d9ce7; background-color: #ffffff; border: 0px; padding: 1px 0px 1px calc(12px + 0.35ex);"&gt;https://community.nxp.com/docs/DOC-328097&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;when i execute it my ERM reports that the error is injected but the function Machine_check_handler() is not being invoked by IVOR1 WHY?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am using the same assembly files given in the above example for startup and interrupt initialization&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Debugger O/P&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;BEFORE&lt;/STRONG&gt; &lt;BR /&gt;/** Cause an error by read operation */&lt;BR /&gt; test_read = test[0];&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; &lt;STRONG&gt;Core Registers&lt;/STRONG&gt;&lt;BR /&gt;R0 0083DB98 R8 1 R16 0 R24 4004185A ^S+ ^Stack_+&lt;BR /&gt;R1 40080F30 R9 8A R17 0 R25 00857138&lt;BR /&gt;R2 0085F0B4 R10 0 R18 0 R26 0085712C&lt;BR /&gt;R3 02009000 R11 00856FF0 R19 0 R27 00857138&lt;BR /&gt;R4 1000 R12 1 R20 0 R28 40080FB0&lt;BR /&gt;R5 FFE6422C R13 40048000 R21 0 R29 40080F5C&lt;BR /&gt;R6 FFF64000 R14 0 R22 0 R30 40080F64&lt;BR /&gt;R7 1 R15 0 R23 0 R31 1&lt;BR /&gt;--------------------------------------------------------------&lt;BR /&gt;TBL EFB993C2 XER 0 CR 20000000 LR 0083DB98&lt;BR /&gt;TBU F0D20C0C USPRG03F8F507F CTR 4004189E IP 0083DF38&lt;BR /&gt;--------------------------------------------------------------&lt;BR /&gt;SPRG0 BD8EFB97 SRR0 00853360 IVPR 00850000 &lt;STRONG&gt;MSR 02008000&lt;/STRONG&gt;&lt;BR /&gt;SPRG1 590CEEFB SRR1 1000 DEAR 158E0418 PVR 816A0000&lt;BR /&gt;SPRG2 641FABE7 CSRR0 6E9B5AB6 ESR 0 DEC 0BABEAFE&lt;BR /&gt;SPRG3 E3EB176A CSRR1 C43E7793 MCSR 0 DECAR DC6A1668&lt;BR /&gt;SPRG4 B14F767B MCSRR075FE2A71 MCAR 000CF001 TCR 0&lt;BR /&gt;SPRG5 CB65DC71 MCSRR1740EFDBF TSR 0&lt;BR /&gt;SPRG6 E94FF9FD PID 0&lt;BR /&gt;SPRG7 F8A9D1F6&lt;BR /&gt;SPRG8 8DCEC43D UCLE _ SPE S WE _ CE _ EE E PR _&lt;BR /&gt;SPRG9 EFD7A7BF FP _ ME _ DE _ IS _ DS _ RI _&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; EIM - Error Injection Module&lt;BR /&gt; &lt;STRONG&gt;EIMCR 00000001 GEIEN 01: Enabled&lt;/STRONG&gt;&lt;BR /&gt; EICHEN 40000000 EICH0EN 00: Error injection is disabled on Error Injection Channel 0&lt;BR /&gt; &lt;STRONG&gt;EICH1EN 01: Error injection is enabled on Error Injection Channel 1&lt;/STRONG&gt;&lt;BR /&gt; EICH2EN 00: Error injection is disabled on Error Injection Channel 2&lt;BR /&gt; EICH3EN 00: Error injection is disabled on Error Injection Channel 3&lt;BR /&gt; EICH4EN 00: Error injection is disabled on Error Injection Channel 4&lt;BR /&gt; EICH5EN 00: Error injection is disabled on Error Injection Channel 5&lt;BR /&gt; EICHD0_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; EICHD0_WORD1 00000000 B0_3DATA_MASK 00000000&lt;BR /&gt; EICHD0_WORD2 00000000 B4_7DATA_MASK 00000000&lt;BR /&gt; EICHD1_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; &lt;STRONG&gt;EICHD1_WORD1 00000001 B0_3DATA_MASK 00000001&lt;/STRONG&gt;&lt;BR /&gt; EICHD1_WORD2 00000000 B4_7DATA_MASK 00000000&lt;BR /&gt; EICHD2_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; EICHD2_WORD1 00000000 B0_3DATA_MASK 00000000&lt;BR /&gt; EICHD2_WORD2 ???????? B4_7DATA_MASK&lt;BR /&gt; EICHD3_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; EICHD3_WORD1 00000000 B0_3DATA_MASK 00000000&lt;BR /&gt; EICHD3_WORD2 00000000 B4_7DATA_MASK 00000000&lt;BR /&gt; EICHD4_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; EICHD4_WORD1 00000000 B0_3DATA_MASK 00000000&lt;BR /&gt; EICHD4_WORD2 00000000 B4_7DATA_MASK 00000000&lt;BR /&gt; EICHD5_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; EICHD5_WORD1 00000000 B0_3DATA_MASK 00000000&lt;BR /&gt; EICHD5_WORD2 00000000 B4_7DATA_MASK 00000000&lt;/P&gt;&lt;P&gt;eMIOS - Configurable Enhanced Modular IO Subsystems&lt;/P&gt;&lt;P&gt;EQADC - Enhanced Queued Analog-to-Digital Converters&lt;/P&gt;&lt;P&gt;ERM - Error Reporting Module&lt;BR /&gt; CR0 00000000 ESCIE0 00: Interrupt notification of Memory 0 single-bit correction events is disabled&lt;BR /&gt; ENCIE0 00: Interrupt notification of Memory 0 non-correctable error events is disabled&lt;BR /&gt; ESCIE1 00: Interrupt notification of Memory 1 single-bit correction events is disabled&lt;BR /&gt; ENCIE1 00: Interrupt notification of Memory 1 non-correctable error events is disabled&lt;BR /&gt; ESCIE2 00: Interrupt notification of Memory 2 single-bit correction events is disabled&lt;BR /&gt; ENCIE2 00: Interrupt notification of Memory 2 non-correctable error events is disabled&lt;BR /&gt; ESCIE3 00: Interrupt notification of Memory 3 single-bit correction events is disabled&lt;BR /&gt; ENCIE3 00: Interrupt notification of Memory 3 non-correctable error events is disabled&lt;BR /&gt; ESCIE4 00: Interrupt notification of Memory 4 single-bit correction events is disabled&lt;BR /&gt; ENCIE4 00: Interrupt notification of Memory 4 non-correctable error events is disabled&lt;BR /&gt; ESCIE5 00: Interrupt notification of Memory 5 single-bit correction events is disabled&lt;BR /&gt; ENCIE5 00: Interrupt notification of Memory 5 non-correctable error events is disabled&lt;BR /&gt; ESCIE6 00: Interrupt notification of Memory 6 single-bit correction events is disabled&lt;BR /&gt; ENCIE6 00: Interrupt notification of Memory 6 non-correctable error events is disabled&lt;BR /&gt; ESCIE7 00: Interrupt notification of Memory 7 single-bit correction events is disabled&lt;BR /&gt; ENCIE7 00: Interrupt notification of Memory 7 non-correctable error events is disabled&lt;BR /&gt; CR1 00000000 ESCIE8 00: Interrupt notification of Memory 8 single-bit correction events is disabled&lt;BR /&gt; ENCIE8 00: Interrupt notification of Memory 8 non-correctable error events is disabled&lt;BR /&gt; ESCIE9 00: Interrupt notification of Memory 9 single-bit correction events is disabled&lt;BR /&gt; ENCIE9 00: Interrupt notification of Memory 9 non-correctable error events is disabled&lt;BR /&gt; ESCIE10 00: Interrupt notification of Memory 10 single-bit correction events is disabled&lt;BR /&gt; ENCIE10 00: Interrupt notification of Memory 10 non-correctable error events is disabled&lt;BR /&gt; ESCIE11 00: Interrupt notification of Memory 11 single-bit correction events is disabled&lt;BR /&gt; ENCIE11 00: Interrupt notification of Memory 11 non-correctable error events is disabled&lt;BR /&gt; ESCIE12 00: Interrupt notification of Memory 12 single-bit correction events is disabled&lt;BR /&gt; ENCIE12 00: Interrupt notification of Memory 12 non-correctable error events is disabled&lt;BR /&gt; ESCIE13 00: Interrupt notification of Memory 13 single-bit correction events is disabled&lt;BR /&gt; ENCIE13 00: Interrupt notification of Memory 13 non-correctable error events is disabled&lt;BR /&gt; ESCIE14 00: Interrupt notification of Memory 14 single-bit correction events is disabled&lt;BR /&gt; ENCIE14 00: Interrupt notification of Memory 14 non-correctable error events is disabled&lt;BR /&gt; ESCIE15 00: Interrupt notification of Memory 15 single-bit correction events is disabled&lt;BR /&gt; ENCIE15 00: Interrupt notification of Memory 15 non-correctable error events is disabled&lt;BR /&gt; CR2 00000000 ESCIE16 00: Interrupt notification of Memory 16 single-bit correction events is disabled&lt;BR /&gt; ENCIE16 00: Interrupt notification of Memory 16 non-correctable error events is disabled&lt;BR /&gt; ESCIE17 00: Interrupt notification of Memory 17 single-bit correction events is disabled&lt;BR /&gt; ENCIE17 00: Interrupt notification of Memory 17 non-correctable error events is disabled&lt;BR /&gt; ESCIE18 00: Interrupt notification of Memory 18 single-bit correction events is disabled&lt;BR /&gt; ENCIE18 00: Interrupt notification of Memory 18 non-correctable error events is disabled&lt;BR /&gt; ESCIE19 00: Interrupt notification of Memory 19 single-bit correction events is disabled&lt;BR /&gt; ENCIE19 00: Interrupt notification of Memory 19 non-correctable error events is disabled&lt;BR /&gt; SR0 00000000 SBC0 00: No single-bit correction event on Memory 0 detected&lt;BR /&gt; NCE0 00: No non-correctable error event on Memory 0 detected&lt;BR /&gt; SBC1 00: No single-bit correction event on Memory 1 detected&lt;BR /&gt; NCE1 00: No non-correctable error event on Memory 1 detected&lt;BR /&gt; SBC2 00: No single-bit correction event on Memory 2 detected&lt;BR /&gt; NCE2 00: No non-correctable error event on Memory 2 detected&lt;BR /&gt; SBC3 00: No single-bit correction event on Memory 3 detected&lt;BR /&gt; NCE3 00: No non-correctable error event on Memory 3 detected&lt;BR /&gt; SBC4 00: No single-bit correction event on Memory 4 detected&lt;BR /&gt; NCE4 00: No non-correctable error event on Memory 4 detected&lt;BR /&gt; SBC5 00: No single-bit correction event on Memory 5 detected&lt;BR /&gt; NCE5 00: No non-correctable error event on Memory 5 detected&lt;BR /&gt; SBC6 00: No single-bit correction event on Memory 6 detected&lt;BR /&gt; NCE6 00: No non-correctable error event on Memory 6 detected&lt;BR /&gt; SBC7 00: No single-bit correction event on Memory 7 detected&lt;BR /&gt; NCE7 00: No non-correctable error event on Memory 7 detected&lt;BR /&gt; SR1 00000000 SBC8 00: No single-bit correction event on Memory 8 detected&lt;BR /&gt; NCE8 00: No non-correctable error event on Memory 8 detected&lt;BR /&gt; SBC9 00: No single-bit correction event on Memory 9 detected&lt;BR /&gt; NCE9 00: No non-correctable error event on Memory 9 detected&lt;BR /&gt; SBC10 00: No single-bit correction event on Memory 10 detected&lt;BR /&gt; NCE10 00: No non-correctable error event on Memory 10 detected&lt;BR /&gt; SBC11 00: No single-bit correction event on Memory 11 detected&lt;BR /&gt; NCE11 00: No non-correctable error event on Memory 11 detected&lt;BR /&gt; SBC12 00: No single-bit correction event on Memory 12 detected&lt;BR /&gt; NCE12 00: No non-correctable error event on Memory 12 detected&lt;BR /&gt; SBC13 00: No single-bit correction event on Memory 13 detected&lt;BR /&gt; NCE13 00: No non-correctable error event on Memory 13 detected&lt;BR /&gt; SBC14 00: No single-bit correction event on Memory 14 detected&lt;BR /&gt; NCE14 00: No non-correctable error event on Memory 14 detected&lt;BR /&gt; SBC15 00: No single-bit correction event on Memory 15 detected&lt;BR /&gt; NCE15 00: No non-correctable error event on Memory 15 detected&lt;BR /&gt; SR2 00000000 SBC16 00: No single-bit correction event on Memory 16 detected&lt;BR /&gt; NCE16 00: No non-correctable error event on Memory 16 detected&lt;BR /&gt; SBC17 00: No single-bit correction event on Memory 17 detected&lt;BR /&gt; NCE17 00: No non-correctable error event on Memory 17 detected&lt;BR /&gt; SBC18 00: No single-bit correction event on Memory 18 detected&lt;BR /&gt; NCE18 00: No non-correctable error event on Memory 18 detected&lt;BR /&gt; SBC19 00: No single-bit correction event on Memory 19 detected&lt;BR /&gt; NCE19 00: No non-correctable error event on Memory 19 detected&lt;BR /&gt; EAR0 00000000 EAR 00000000&lt;BR /&gt; SYN0 00000000 SYNDROME 00&lt;BR /&gt; EAR1 00000000 EAR 00000000&lt;BR /&gt; SYN1 00000000 SYNDROME 00&lt;BR /&gt; EAR2 00000000 EAR 00000000&lt;BR /&gt; SYN2 00000000 SYNDROME 00&lt;BR /&gt; EAR3 00000000 EAR 00000000&lt;BR /&gt; SYN3 00000000 SYNDROME 00&lt;BR /&gt; EAR4 00000000 EAR 00000000&lt;BR /&gt; SYN4 00000000 SYNDROME 00&lt;BR /&gt; EAR5 00000000 EAR 00000000&lt;BR /&gt; SYN5 00000000 SYNDROME 00&lt;BR /&gt; EAR6 00000000 EAR 00000000&lt;BR /&gt; SYN6 00000000 SYNDROME 00&lt;BR /&gt; EAR7 00000000 EAR 00000000&lt;BR /&gt; SYN7 00000000 SYNDROME 00&lt;BR /&gt; EAR8 00000000 EAR 00000000&lt;BR /&gt; SYN8 00000000 SYNDROME 00&lt;BR /&gt; EAR9 00000000 EAR 00000000&lt;BR /&gt; SYN9 00000000 SYNDROME 00&lt;BR /&gt; EAR10 00000000 EAR 00000000&lt;BR /&gt; SYN10 00000000 SYNDROME 00&lt;BR /&gt; EAR11 00000000 EAR 00000000&lt;BR /&gt; SYN11 00000000 SYNDROME 00&lt;BR /&gt; EAR12 00000000 EAR 00000000&lt;BR /&gt; SYN12 00000000 SYNDROME 00&lt;BR /&gt; EAR13 00000000 EAR 00000000&lt;BR /&gt; SYN13 00000000 SYNDROME 00&lt;BR /&gt; EAR14 00000000 EAR 00000000&lt;BR /&gt; SYN14 00000000 SYNDROME 00&lt;BR /&gt; EAR15 00000000 EAR 00000000&lt;BR /&gt; SYN15 00000000 SYNDROME 00&lt;BR /&gt; EAR16 00000000 EAR 00000000&lt;BR /&gt; SYN16 00000000 SYNDROME 00&lt;BR /&gt; EAR17 00000000 EAR 00000000&lt;BR /&gt; SYN17 00000000 SYNDROME 00&lt;BR /&gt; EAR18 00000000 EAR 00000000&lt;BR /&gt; SYN18 00000000 SYNDROME 00&lt;BR /&gt; EAR19 00000000 EAR 00000000&lt;BR /&gt; SYN19 00000000 SYNDROME 00&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;AFTER&lt;/STRONG&gt; &lt;BR /&gt;/** Cause an error by read operation */&lt;BR /&gt; test_read = test[0];&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Core Registers&lt;/P&gt;&lt;P&gt;R0 0083DB98 R8 1 R16 0 R24 4004185A ^S+ ^Stack_+&lt;BR /&gt;R1 40080F30 R9 8A R17 0 R25 00857138&lt;BR /&gt;R2 0085F0B4 R10 0 R18 0 R26 0085712C&lt;BR /&gt;R3 02009000 R11 00856FF0 R19 0 R27 00857138&lt;BR /&gt;R4 1000 R12 1 R20 0 R28 40080FB0&lt;BR /&gt;R5 FFE6422C R13 40048000 R21 0 R29 40080F5C&lt;BR /&gt;R6 FFF64000 R14 0 R22 0 R30 40080F64&lt;BR /&gt;R7 11111111 R15 0 R23 0 R31 1&lt;BR /&gt;--------------------------------------------------------------&lt;BR /&gt;TBL EFB993C2 XER 0 CR 20000000 LR 0083DB98&lt;BR /&gt;TBU F0D20C0C USPRG03F8F507F CTR 4004189E IP 0083DF40&lt;BR /&gt;--------------------------------------------------------------&lt;BR /&gt;SPRG0 BD8EFB97 SRR0 00853360 IVPR 00850000 &lt;STRONG&gt;MSR 02008000&lt;/STRONG&gt;&lt;BR /&gt;SPRG1 590CEEFB SRR1 1000 DEAR 158E0418 PVR 816A0000&lt;BR /&gt;SPRG2 641FABE7 CSRR0 6E9B5AB6 ESR 0 DEC 0BABEAFE&lt;BR /&gt;SPRG3 E3EB176A CSRR1 C43E7793 MCSR 0 DECAR DC6A1668&lt;BR /&gt;SPRG4 B14F767B MCSRR075FE2A71 MCAR 000CF001 TCR 0&lt;BR /&gt;SPRG5 CB65DC71 MCSRR1740EFDBF TSR 0&lt;BR /&gt;SPRG6 E94FF9FD PID 0&lt;BR /&gt;SPRG7 F8A9D1F6&lt;BR /&gt;SPRG8 8DCEC43D UCLE _ SPE S WE _ CE _ EE E PR _&lt;BR /&gt;SPRG9 EFD7A7BF FP _ ME _ DE _ IS _ DS _ RI _&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;EIM - Error Injection Module&lt;BR /&gt; &lt;STRONG&gt;EIMCR 00000001 GEIEN 01: Enabled&lt;/STRONG&gt;&lt;BR /&gt; EICHEN 40000000 EICH0EN 00: Error injection is disabled on Error Injection Channel 0&lt;BR /&gt; &lt;STRONG&gt;EICH1EN 01: Error injection is enabled on Error Injection Channel 1&lt;/STRONG&gt;&lt;BR /&gt; EICH2EN 00: Error injection is disabled on Error Injection Channel 2&lt;BR /&gt; EICH3EN 00: Error injection is disabled on Error Injection Channel 3&lt;BR /&gt; EICH4EN 00: Error injection is disabled on Error Injection Channel 4&lt;BR /&gt; EICH5EN 00: Error injection is disabled on Error Injection Channel 5&lt;BR /&gt; EICHD0_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; EICHD0_WORD1 00000000 B0_3DATA_MASK 00000000&lt;BR /&gt; EICHD0_WORD2 00000000 B4_7DATA_MASK 00000000&lt;BR /&gt; EICHD1_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; &lt;STRONG&gt;EICHD1_WORD1 00000001 B0_3DATA_MASK 00000001&lt;/STRONG&gt;&lt;BR /&gt; EICHD1_WORD2 00000000 B4_7DATA_MASK 00000000&lt;BR /&gt; EICHD2_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; EICHD2_WORD1 00000000 B0_3DATA_MASK 00000000&lt;BR /&gt; EICHD2_WORD2 ???????? B4_7DATA_MASK&lt;BR /&gt; EICHD3_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; EICHD3_WORD1 00000000 B0_3DATA_MASK 00000000&lt;BR /&gt; EICHD3_WORD2 00000000 B4_7DATA_MASK 00000000&lt;BR /&gt; EICHD4_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; EICHD4_WORD1 00000000 B0_3DATA_MASK 00000000&lt;BR /&gt; EICHD4_WORD2 00000000 B4_7DATA_MASK 00000000&lt;BR /&gt; EICHD5_WORD0 00000000 CHKBIT_MASK 00&lt;BR /&gt; EICHD5_WORD1 00000000 B0_3DATA_MASK 00000000&lt;BR /&gt; EICHD5_WORD2 00000000 B4_7DATA_MASK 00000000&lt;/P&gt;&lt;P&gt;eMIOS - Configurable Enhanced Modular IO Subsystems&lt;/P&gt;&lt;P&gt;EQADC - Enhanced Queued Analog-to-Digital Converters&lt;/P&gt;&lt;P&gt;ERM - Error Reporting Module&lt;BR /&gt; CR0 00000000 ESCIE0 00: Interrupt notification of Memory 0 single-bit correction events is disabled&lt;BR /&gt; ENCIE0 00: Interrupt notification of Memory 0 non-correctable error events is disabled&lt;BR /&gt; ESCIE1 00: Interrupt notification of Memory 1 single-bit correction events is disabled&lt;BR /&gt; ENCIE1 00: Interrupt notification of Memory 1 non-correctable error events is disabled&lt;BR /&gt; ESCIE2 00: Interrupt notification of Memory 2 single-bit correction events is disabled&lt;BR /&gt; ENCIE2 00: Interrupt notification of Memory 2 non-correctable error events is disabled&lt;BR /&gt; ESCIE3 00: Interrupt notification of Memory 3 single-bit correction events is disabled&lt;BR /&gt; ENCIE3 00: Interrupt notification of Memory 3 non-correctable error events is disabled&lt;BR /&gt; ESCIE4 00: Interrupt notification of Memory 4 single-bit correction events is disabled&lt;BR /&gt; ENCIE4 00: Interrupt notification of Memory 4 non-correctable error events is disabled&lt;BR /&gt; ESCIE5 00: Interrupt notification of Memory 5 single-bit correction events is disabled&lt;BR /&gt; ENCIE5 00: Interrupt notification of Memory 5 non-correctable error events is disabled&lt;BR /&gt; ESCIE6 00: Interrupt notification of Memory 6 single-bit correction events is disabled&lt;BR /&gt; ENCIE6 00: Interrupt notification of Memory 6 non-correctable error events is disabled&lt;BR /&gt; ESCIE7 00: Interrupt notification of Memory 7 single-bit correction events is disabled&lt;BR /&gt; ENCIE7 00: Interrupt notification of Memory 7 non-correctable error events is disabled&lt;BR /&gt; CR1 00000000 ESCIE8 00: Interrupt notification of Memory 8 single-bit correction events is disabled&lt;BR /&gt; ENCIE8 00: Interrupt notification of Memory 8 non-correctable error events is disabled&lt;BR /&gt; ESCIE9 00: Interrupt notification of Memory 9 single-bit correction events is disabled&lt;BR /&gt; ENCIE9 00: Interrupt notification of Memory 9 non-correctable error events is disabled&lt;BR /&gt; ESCIE10 00: Interrupt notification of Memory 10 single-bit correction events is disabled&lt;BR /&gt; ENCIE10 00: Interrupt notification of Memory 10 non-correctable error events is disabled&lt;BR /&gt; ESCIE11 00: Interrupt notification of Memory 11 single-bit correction events is disabled&lt;BR /&gt; ENCIE11 00: Interrupt notification of Memory 11 non-correctable error events is disabled&lt;BR /&gt; ESCIE12 00: Interrupt notification of Memory 12 single-bit correction events is disabled&lt;BR /&gt; ENCIE12 00: Interrupt notification of Memory 12 non-correctable error events is disabled&lt;BR /&gt; ESCIE13 00: Interrupt notification of Memory 13 single-bit correction events is disabled&lt;BR /&gt; ENCIE13 00: Interrupt notification of Memory 13 non-correctable error events is disabled&lt;BR /&gt; ESCIE14 00: Interrupt notification of Memory 14 single-bit correction events is disabled&lt;BR /&gt; ENCIE14 00: Interrupt notification of Memory 14 non-correctable error events is disabled&lt;BR /&gt; ESCIE15 00: Interrupt notification of Memory 15 single-bit correction events is disabled&lt;BR /&gt; ENCIE15 00: Interrupt notification of Memory 15 non-correctable error events is disabled&lt;BR /&gt; CR2 00000000 ESCIE16 00: Interrupt notification of Memory 16 single-bit correction events is disabled&lt;BR /&gt; ENCIE16 00: Interrupt notification of Memory 16 non-correctable error events is disabled&lt;BR /&gt; ESCIE17 00: Interrupt notification of Memory 17 single-bit correction events is disabled&lt;BR /&gt; ENCIE17 00: Interrupt notification of Memory 17 non-correctable error events is disabled&lt;BR /&gt; ESCIE18 00: Interrupt notification of Memory 18 single-bit correction events is disabled&lt;BR /&gt; ENCIE18 00: Interrupt notification of Memory 18 non-correctable error events is disabled&lt;BR /&gt; ESCIE19 00: Interrupt notification of Memory 19 single-bit correction events is disabled&lt;BR /&gt; ENCIE19 00: Interrupt notification of Memory 19 non-correctable error events is disabled&lt;BR /&gt; SR0 00000000 SBC0 00: No single-bit correction event on Memory 0 detected&lt;BR /&gt; NCE0 00: No non-correctable error event on Memory 0 detected&lt;BR /&gt; SBC1 00: No single-bit correction event on Memory 1 detected&lt;BR /&gt; NCE1 00: No non-correctable error event on Memory 1 detected&lt;BR /&gt; SBC2 00: No single-bit correction event on Memory 2 detected&lt;BR /&gt; NCE2 00: No non-correctable error event on Memory 2 detected&lt;BR /&gt; SBC3 00: No single-bit correction event on Memory 3 detected&lt;BR /&gt; NCE3 00: No non-correctable error event on Memory 3 detected&lt;BR /&gt; SBC4 00: No single-bit correction event on Memory 4 detected&lt;BR /&gt; NCE4 00: No non-correctable error event on Memory 4 detected&lt;BR /&gt; SBC5 00: No single-bit correction event on Memory 5 detected&lt;BR /&gt; NCE5 00: No non-correctable error event on Memory 5 detected&lt;BR /&gt; SBC6 00: No single-bit correction event on Memory 6 detected&lt;BR /&gt; NCE6 00: No non-correctable error event on Memory 6 detected&lt;BR /&gt; SBC7 00: No single-bit correction event on Memory 7 detected&lt;BR /&gt; NCE7 00: No non-correctable error event on Memory 7 detected&lt;BR /&gt; SR1 00000080 SBC8 00: No single-bit correction event on Memory 8 detected&lt;BR /&gt; NCE8 00: No non-correctable error event on Memory 8 detected&lt;BR /&gt; SBC9 00: No single-bit correction event on Memory 9 detected&lt;BR /&gt; NCE9 00: No non-correctable error event on Memory 9 detected&lt;BR /&gt; SBC10 00: No single-bit correction event on Memory 10 detected&lt;BR /&gt; NCE10 00: No non-correctable error event on Memory 10 detected&lt;BR /&gt; SBC11 00: No single-bit correction event on Memory 11 detected&lt;BR /&gt; NCE11 00: No non-correctable error event on Memory 11 detected&lt;BR /&gt; SBC12 00: No single-bit correction event on Memory 12 detected&lt;BR /&gt; NCE12 00: No non-correctable error event on Memory 12 detected&lt;BR /&gt; SBC13 00: No single-bit correction event on Memory 13 detected&lt;BR /&gt; NCE13 00: No non-correctable error event on Memory 13 detected&lt;BR /&gt; &lt;STRONG&gt;SBC14 01: Single-bit correction event on Memory 14 detected&lt;/STRONG&gt;&lt;BR /&gt; NCE14 00: No non-correctable error event on Memory 14 detected&lt;BR /&gt; SBC15 00: No single-bit correction event on Memory 15 detected&lt;BR /&gt; NCE15 00: No non-correctable error event on Memory 15 detected&lt;BR /&gt; SR2 00000000 SBC16 00: No single-bit correction event on Memory 16 detected&lt;BR /&gt; NCE16 00: No non-correctable error event on Memory 16 detected&lt;BR /&gt; SBC17 00: No single-bit correction event on Memory 17 detected&lt;BR /&gt; NCE17 00: No non-correctable error event on Memory 17 detected&lt;BR /&gt; SBC18 00: No single-bit correction event on Memory 18 detected&lt;BR /&gt; NCE18 00: No non-correctable error event on Memory 18 detected&lt;BR /&gt; SBC19 00: No single-bit correction event on Memory 19 detected&lt;BR /&gt; NCE19 00: No non-correctable error event on Memory 19 detected&lt;BR /&gt; EAR0 00000000 EAR 00000000&lt;BR /&gt; SYN0 00000000 SYNDROME 00&lt;BR /&gt; EAR1 00000000 EAR 00000000&lt;BR /&gt; SYN1 00000000 SYNDROME 00&lt;BR /&gt; EAR2 00000000 EAR 00000000&lt;BR /&gt; SYN2 00000000 SYNDROME 00&lt;BR /&gt; EAR3 00000000 EAR 00000000&lt;BR /&gt; SYN3 00000000 SYNDROME 00&lt;BR /&gt; EAR4 00000000 EAR 00000000&lt;BR /&gt; SYN4 00000000 SYNDROME 00&lt;BR /&gt; EAR5 00000000 EAR 00000000&lt;BR /&gt; SYN5 00000000 SYNDROME 00&lt;BR /&gt; EAR6 00000000 EAR 00000000&lt;BR /&gt; SYN6 00000000 SYNDROME 00&lt;BR /&gt; EAR7 00000000 EAR 00000000&lt;BR /&gt; SYN7 00000000 SYNDROME 00&lt;BR /&gt; EAR8 00000000 EAR 00000000&lt;BR /&gt; SYN8 00000000 SYNDROME 00&lt;BR /&gt; EAR9 00000000 EAR 00000000&lt;BR /&gt; SYN9 00000000 SYNDROME 00&lt;BR /&gt; EAR10 00000000 EAR 00000000&lt;BR /&gt; SYN10 00000000 SYNDROME 00&lt;BR /&gt; EAR11 00000000 EAR 00000000&lt;BR /&gt; SYN11 00000000 SYNDROME 00&lt;BR /&gt; EAR12 00000000 EAR 00000000&lt;BR /&gt; SYN12 00000000 SYNDROME 00&lt;BR /&gt; EAR13 00000000 EAR 00000000&lt;BR /&gt; SYN13 00000000 SYNDROME 00&lt;BR /&gt; EAR14 40040790 EAR 40040790&lt;BR /&gt; SYN14 46000000 SYNDROME 46&lt;BR /&gt; EAR15 00000000 EAR 00000000&lt;BR /&gt; SYN15 00000000 SYNDROME 00&lt;BR /&gt; EAR16 00000000 EAR 00000000&lt;BR /&gt; SYN16 00000000 SYNDROME 00&lt;BR /&gt; EAR17 00000000 EAR 00000000&lt;BR /&gt; SYN17 00000000 SYNDROME 00&lt;BR /&gt; EAR18 00000000 EAR 00000000&lt;BR /&gt; SYN18 00000000 SYNDROME 00&lt;BR /&gt; EAR19 00000000 EAR 00000000&lt;BR /&gt; SYN19 00000000 SYNDROME 00&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/davidtosenovjan"&gt;davidtosenovjan&lt;/A&gt;&amp;nbsp;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/PetrS"&gt;PetrS&lt;/A&gt;&amp;nbsp; Please help&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank You&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Jun 2019 06:26:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/No-IVOR1-exception-even-after-ERM-module-reports-errors/m-p/931814#M13971</guid>
      <dc:creator>ignatiusmichael</dc:creator>
      <dc:date>2019-06-17T06:26:10Z</dc:date>
    </item>
    <item>
      <title>Re: No IVOR1 exception even after ERM module reports errors</title>
      <link>https://community.nxp.com/t5/MPC5xxx/No-IVOR1-exception-even-after-ERM-module-reports-errors/m-p/931815#M13972</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have just downloaded and tested Davids code and it is reporting in ERM after 1-bit error is injected as expected.&lt;/P&gt;&lt;P&gt;See my screenshot bellow:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/87277i10D133187C435318/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I did no modification to it, just run it.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt;Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Jun 2019 12:36:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/No-IVOR1-exception-even-after-ERM-module-reports-errors/m-p/931815#M13972</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2019-06-17T12:36:40Z</dc:date>
    </item>
    <item>
      <title>Re: No IVOR1 exception even after ERM module reports errors</title>
      <link>https://community.nxp.com/t5/MPC5xxx/No-IVOR1-exception-even-after-ERM-module-reports-errors/m-p/931816#M13973</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Peter,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for you speedy reply. Even i am able to get&amp;nbsp;&lt;STRONG style="color: #51626f; background-color: #ffffff; border: 0px; font-weight: bold;"&gt;SBC14 01: Single-bit correction event on Memory 14 detected&amp;nbsp;&lt;/STRONG&gt;as shown in the log file above but in my case IVOR1 exception is not being raised and machine_Check_Handler is not being called. i have even attatched my core registers log for your reference. my&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;STRONG style="color: #51626f; background-color: #ffffff; border: 0px; font-weight: bold;"&gt;MSR 02008000&amp;nbsp;&amp;nbsp;&lt;/STRONG&gt;.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please help how can i get my IVOR1 handler to work i am using the same startup files as given in the example project.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you,&lt;/P&gt;&lt;P&gt;Regards&amp;nbsp;&lt;/P&gt;&lt;P&gt;Michael Jihan&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 18 Jun 2019 03:45:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/No-IVOR1-exception-even-after-ERM-module-reports-errors/m-p/931816#M13973</guid>
      <dc:creator>ignatiusmichael</dc:creator>
      <dc:date>2019-06-18T03:45:47Z</dc:date>
    </item>
    <item>
      <title>Re: No IVOR1 exception even after ERM module reports errors</title>
      <link>https://community.nxp.com/t5/MPC5xxx/No-IVOR1-exception-even-after-ERM-module-reports-errors/m-p/931817#M13974</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;That's correct.&lt;/P&gt;&lt;P&gt;Single bit will not cause exception. As the single bit event is automatically repaired by ECC machine.&lt;/P&gt;&lt;P&gt;However multibit ECC will cause IVOR1.&lt;/P&gt;&lt;P&gt;For multibit you have to enable it in example code.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;regards,&lt;/P&gt;&lt;P&gt;Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 20 Jun 2019 08:13:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/No-IVOR1-exception-even-after-ERM-module-reports-errors/m-p/931817#M13974</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2019-06-20T08:13:05Z</dc:date>
    </item>
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