topic Re: What is the relationship between FMPLL and BIUCR? in MPC5xxx

What is the relationship between FMPLL and BIUCR?

tgc-yilmaz — Tue, 16 Jul 2019 20:35:40 GMT

Hello,

I'm using a MPC5644A and want to set the maximum value of the system frequency (150MHz). However,

If the system frequency is set to values greater than 82MHz, I have to make the following definitions in the __ppc_eabi_init file. Why are these definitions made in __ppc_eabi_init file? What is the relationship between FMPLL and BIUCR?

Thank you for your help...

Re: What is the relationship between FMPLL and BIUCR?

lukaszadrapa — Wed, 17 Jul 2019 04:53:38 GMT

Hi,

there are APC, WWSC and RWSC bit fields in the BIUCR which are used to configure flash wait states:

And in the datasheet:

For 150MHz, there should be 0x----9C--

You can re-use initialization code from:

https://community.nxp.com/docs/DOC-101455

Regards,

Lukas

Re: What is the relationship between FMPLL and BIUCR?

tgc-yilmaz — Wed, 17 Jul 2019 19:31:21 GMT

Hello Lukas Zadrapa,

Thank you for your answer. I am asking for be sure. We do these definitions in order to be able to read properly from flash at higher operating frequencies. In this way, we prevent the error in the code by associating the flash reading speed with the operating frequency.

Regards,

Re: What is the relationship between FMPLL and BIUCR?

lukaszadrapa — Thu, 18 Jul 2019 07:23:37 GMT

Yes, that's correct. The flash is not so fast, so if higher system clock is used, it's necessary to wait until the flash is able to provide requested data - this is managed by flash wait states. By default, the flash wait state are always configured to maximum. For best performance, it's necessary to follow the mentioned table from the datasheet and configure it appropriately.

Regards,

Lukas