machine check exception after generating multi bit error (MPC5777C) while testing SRAM

manaswini1317 — Sat, 10 Aug 2019 13:38:43 GMT

I've been working on EIM_ERM module lately. I could see that a machine check exception occurs after generating a multi bit error. Although I've tried to handle the exception by writing a logic which instructs to move to next instrcution. Surprisingly,the next instruction also goes into handler and then the process repeats.I tried disabling the global enable and bit in EIMCR also. Below is the handler:

void machine_exception(VectorId vector,const void *stack_ptr)
{
MPC::ErrorInjectionModule eim(0xFFF64000UL);

Uint32 new_xsrr0 = 0UL;
eim.disable_injection();
new_xsrr0 = get_xsrr0((Uint32 *)stack_ptr, std_context_size) + 4UL;
set_xsrr0((Uint32 *)stack_ptr, std_context_size, new_xsrr0);
return;
}

PFA of the registers after exception has occured

Kindly let me know if I am going wrong somewhere.

Re: machine check exception after generating multi bit error (MPC5777C) while testing SRAM

petervlna — Mon, 12 Aug 2019 10:55:52 GMT

Hi,

After injecting the multibit ECC fault to RAM:

So, once you inject ECC multibit error you have to care about IVOR1 or 0. Depends on your micro settings.

If you do not serve it the device will be reset.

For correct servicing please refer to chapter 5 -> Non-correctable ECC error servicing

of application note:

https://community.nxp.com/docs/DOC-103300

regards,

Peter

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machine check exception after generating multi bit error (MPC5777C) while testing SRAM

Re: machine check exception after generating multi bit error (MPC5777C) while testing SRAM