topic Cache enabled in kernel mode but disabled in user mode in MPC5xxx https://community.nxp.com/t5/MPC5xxx/Cache-enabled-in-kernel-mode-but-disabled-in-user-mode/m-p/877462#M12892 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P>I am working on the e200z7 provided by the MPC5777C board.</P><P>I am currently having issues with the L1 caches. The caches are used by the kernel (both instruction and data, with write allocation policy on, in write-through mode).</P><P>However, when switching to user mode, the cache is not used at all. We checked the MMU entries flag and the cache is not inhibit for the addresses we access.</P><P></P><P>Do you have any other recommendation to fix this issue?</P><P></P><P>Regards,</P><P>Alexy</P></BODY></HTML> Wed, 20 Feb 2019 22:31:32 GMT alexy_torres-au 2019-02-20T22:31:32Z Cache enabled in kernel mode but disabled in user mode https://community.nxp.com/t5/MPC5xxx/Cache-enabled-in-kernel-mode-but-disabled-in-user-mode/m-p/877462#M12892 <HTML><HEAD></HEAD><BODY><P>Hello,</P><P></P><P>I am working on the e200z7 provided by the MPC5777C board.</P><P>I am currently having issues with the L1 caches. The caches are used by the kernel (both instruction and data, with write allocation policy on, in write-through mode).</P><P>However, when switching to user mode, the cache is not used at all. We checked the MMU entries flag and the cache is not inhibit for the addresses we access.</P><P></P><P>Do you have any other recommendation to fix this issue?</P><P></P><P>Regards,</P><P>Alexy</P></BODY></HTML> Wed, 20 Feb 2019 22:31:32 GMT https://community.nxp.com/t5/MPC5xxx/Cache-enabled-in-kernel-mode-but-disabled-in-user-mode/m-p/877462#M12892 alexy_torres-au 2019-02-20T22:31:32Z