MPC5xxx中的主题 Re: Double Switching PWMs

Double Switching PWMs

boshimao — Wed, 19 Sep 2018 12:08:13 GMT

My chip is MPC5643L. In the "center-aligned and complementary PWM" mode, the IPOL bit of the register MCTRL is 0, the PWMB is from the complementary pair, and the VAL4 and VAL5 are unused. Can I use the "double switch" function in this mode?

Re: Double Switching PWMs

PetrS — Thu, 20 Sep 2018 09:56:19 GMT

Hi,

yes, you can. If double switching is enabled (CTRL1[DBLEN]=1), then the DBLPWM signal is used for deadtime logic, regardless of setting the MCTRL[IPOLx] and complementary signals will be generated based on DBLPWM.

BR, Petr

Re: Double Switching PWMs

boshimao — Thu, 20 Sep 2018 13:35:44 GMT

Thank you. Ask another question, I write 0x0C05 to register CTRL1. The PWM register INIT is -100, the register VAL0 is 0, the register VAL1 is 100. In the red circle 1, I calculate the duty cycle is 20%, and the PWM waveform should be a or b or something else, as shown in the following figure. The reference manual is a bit questionable. I mainly want to know how LDMOD affects PWM.

Re: Double Switching PWMs

boshimao — Mon, 24 Sep 2018 11:32:51 GMT

hi,Please explain it to me, thank you.

Re: Double Switching PWMs

PetrS — Mon, 24 Sep 2018 12:33:50 GMT

Hi,

LDMOD bit specify when the buffered registers are loaded with new value.

For LDMOD=1 registers are loaded and take effect immediately after LDOK is set,

for LDMOD=0 reagisters are loaded and take effect at the next PWM reload if LDOK is set.

So the PWM will be generated depending on time when LDOK is set. With LDMOD=1 you can simply miss the edge.

BR. Petr