MPC5xxxのトピックRe: MPC5644 Multi-Layer AHB Crossbar Switch (XBAR) setting

MPC5644 Multi-Layer AHB Crossbar Switch (XBAR) setting

miroslav_pesta — Wed, 12 Sep 2018 10:29:40 GMT

Hello

We have in project some issue with DMA and EQADC, first i describe situation:

We are cyclicaly reading one ADC queue of channels (command fifo…), conversion is triggered by EMIOS timer and commands and results are transfered to and from ADC via DMA. Results are saved in cyclical buffer in RAM with 100 samples per channel stored (for some filterin purpouses…).

Now the problem is that in some situations, it looks like one or two channels are skiped during saving results, so value from channel 6 ends up in place of channel 5, ch. 5 in place of ch. 4 etc.

Situations where this happend are with heavy trafic on internal bus (complicated rewriting of some big structures in RAM, stress tests when cache is cyclicaly invalidated…) so i belive it is caused by some prioritization on internal bus.

Originaly we had following setting of XBAR (for slaves RAM and PBRIDGE):

E200z4 (Instruction) M0 : 0

E200z4 (Data/Nexus) M1 : 1

eDMA M4 : 2

When i set DMA to be highest priority and shift acordingly priorities of core (instructions and data..) it solved our problem.

Now, my question is: Is this new setting OK for HW? Can there be some unexpected consequences of this setting?

Thanks for your help

Re: MPC5644 Multi-Layer AHB Crossbar Switch (XBAR) setting

davidtosenovjan — Thu, 13 Sep 2018 17:08:36 GMT

Hi, EQADC result swap may have different reason. See following document, I have prepared:
https://community.nxp.com/docs/DOC-329779

One yet note that result swap can also be caused by abort feature (ICEAn=1) - I can give you further details if needed.

Re: MPC5644 Multi-Layer AHB Crossbar Switch (XBAR) setting

miroslav_pesta — Fri, 14 Sep 2018 05:27:44 GMT

Hello

In our problematic case, in the command queue only ADC0 is used and we have ICEAn set to 0. Also, when i reconfigured the XBAR priorities, problem is gone.

Additionaly, situations when this issue will happen are wery bus usage heavy - cyclic invalidation of chache cause lot of data reading, the rewriting of complicated datastructures also need bus a lot (and i think it is not much optimized, unfortunately that is out of my hands).

Overall it realy looks like bus prioriti problem (espetialy because priority change fix it) so my main concern is, if this new setting of bus priorities can cause some other issues I can´t think of.

Again, thanks for your help.

Re: MPC5644 Multi-Layer AHB Crossbar Switch (XBAR) setting

davidtosenovjan — Mon, 17 Sep 2018 12:18:24 GMT

That's interesting. Having highest for DMA is correct configuration of XBAR, typically it is being configured this way. But I am not sure if this can cause result swap. Actually in your case apparently it is not swap, but loosing of some data.

It would be nice to eQADC registers in the error situation whether underflow/overflow does not happen. If yes, you are right and the issue can be solved by proper XBAR priority setting.