topic Re: AIPS & MPU in MPC5777C in MPC5xxx

AIPS & MPU in MPC5777C

yashkumar — Wed, 11 Jul 2018 09:54:52 GMT

Hi All,

I have two application APP_0(TRUSTED) and APP_1(NON_TRUSTED).

I have configured APP_0 as trusted application and given access to all memory area.
and configure memory block as given manner:
/* Internal RAM (XBAR Slave Port 2 (192KB) )*/
MPU0.RGD[0].WORD0.R = 0x40010000; /* Start address */
MPU0.RGD[0].WORD1.R = 0x4003FFFF; /* End address */
MPU0.RGD[0].WORD2.R = 0x0000003F; /* Read-write-execute allowed for all master */
MPU0.RGD[0].WORD3.R = 0xFF000001; /* Mark descriptor as valid */

/* Peripheral Bridge A Registers */
MPU0.RGD[1].WORD0.R = 0xC3E00000; /* Start address */
MPU0.RGD[1].WORD1.R = 0xFFDFFFFF; /* End address */
MPU0.RGD[1].WORD2.R = 0x0000003F; /* Read-write-execute allowed for all master */
MPU0.RGD[1].WORD3.R = 0xFF000001; /* Mark descriptor as valid */

/* Peripheral Bridge B Registers */
MPU1.RGD[0].WORD0.R = 0xFFE00000; /* Start address */
MPU1.RGD[0].WORD1.R = 0xFFFFFFFF; /* End address */
MPU1.RGD[0].WORD2.R = 0x0000003F; /* Read-write-execute allowed for all master */
MPU1.RGD[0].WORD3.R = 0xFF000001; /* Mark descriptor as valid */

/* For STACK (XBAR Slave Port 4 (256 KB)) )*/
MPU1.RGD[1].WORD0.R = 0x40010000; /* Start address */
MPU1.RGD[1].WORD1.R = 0x4003FFFF; /* End address */
MPU1.RGD[1].WORD2.R = 0x0000003F; /* Read-write-execute allowed for all master */
MPU1.RGD[1].WORD3.R = 0xFF000001; /* Mark descriptor as valid */

MPU1.CESR.B.VLD = 1; /* Enable MPU1 */

MPU0.CESR.B.VLD = 1; /* Enable MPU0 */

But, to APP_1(NON_TRUSTED), i have given access of few area of RAM-

/* Internal RAM of (XBAR Slave Port 2 )*/
MPU0.RGD[2].WORD0.R = 0x40010200; /* Start address */
MPU0.RGD[2].WORD1.R = 0x40010300; /* End address */
MPU0.RGD[2].WORD2.R = 0x0000003F; /* Read-write-execute allowed for all master */
MPU0.RGD[2].WORD3.R = 0x01000001; /* Mark descriptor as valid */

and

/* For STACK of (XBAR Slave Port 4 )*/
MPU1.RGD[2].WORD0.R = 0x40010400; /* Start address */
MPU1.RGD[2].WORD1.R = 0x40000FFF; /* End address */
MPU1.RGD[2].WORD2.R = 0x0000003F; /* Read-write-execute allowed for all master */
MPU1.RGD[2].WORD3.R = 0x01000001; /* Mark descriptor as valid */

And no memory block configured for Peripheral area.

But, when APP_1 runs, i want to provide access of Peripheral area, with the help of AIPS.
If this application(APP_1 ) having variable (PHERIPHEARL ACCESS = TURE)

and i want to provide access, with the help of AIPS, what i have configured below:

AIPS0_MPRA = 0x70000000;

AIPS0_MPRB = 0x00000000;

AIPS0_PACRA =0x44444444;

AIPS0_PACRB =0x44000444;

(so for APP_1, i want allow access from Peripheral XBAR to STM_A only)

but i am getting memory fault when accessing any from XBAR to STM_A .

could you please help me .

Thanks!

Re: AIPS & MPU in MPC5777C

EAlepins — Mon, 16 Jul 2018 20:31:33 GMT

Not answering directly your question, but:

- On MPU0.RGD[0], I don't see the point of setting WORD3.PID and PIDMASK fields because they will be ignored since all your MPU0.RGD[0].WORD2.MxPE fields are zero... Same issue for your other MPU regions.

- MPU1.RGD[0] is wrong since it tries to cover the first half the RAM. MPU0 controls the first half; MPU1 controls the second.

- Does your core MMU (not the MPU) allow accesses to the XBAR registers and STM_A registers?

- Is APP_1 running in Supervisor mode?

Étienne

Re: AIPS & MPU in MPC5777C

yashkumar — Tue, 17 Jul 2018 15:11:09 GMT

Hi Etienne,
Thanks for your response.
I have ordered the RGD[x](region numbers).

1.On MPU0.RGD[0], I don't see the point of setting WORD3..................Same issue for your other MPU regions
* In every Block Configuration i have set the PID( 0xFF for Trusted Application and 0x01 for non trusted application) in WORD3.PID.
* Yes, i did not set PIDMASK, what is role of PIDMASK bits.
* For WORD2.MxPE, As i am using only CORE0 as master, i have set the
M0PE bit as it is (0x3F).I am sorry for, there was typing misktake for WORD2 in each memory block configuration, i have modified that.
2. MPU1.RGD[0] is wrong since it tries to cover the first half the RAM. .....................controls the second.
* I have mapped SRAM(XBAR Slave Port2,192 KB) for data(R/W) in linker file.
* I am not using Standby RAM(64KB).
* I have mapped SRAM( XBAR Slave Port 4,256 KB) for complete stack area.
Is i am doing any thing wrong, please guide.
3.Does your core MMU (not the MPU) allow accesses to the XBAR registers and STM_A registers?
* Does we need to change any control registor in MMU.
Which register, and how to do that.
I am new for this , please guide me.
4.Is APP_1 running in Supervisor mode?

* No, APP_1 is running in USER mode.(PS bit in MSR is 1).

Please give your feedback.

Regards,
Dspic

Re: AIPS & MPU in MPC5777C

EAlepins — Tue, 17 Jul 2018 16:00:29 GMT

2. Regions in MPU0 can only control access to the first 256K of RAM (and MPU1 controls the second half). So to control access to region 0x40010000 to 0x4003FFFF, you should use an MPU0 region, not an MPU1 region.

3. By default (if you have not changed the core MMU configuration), the BAM's configuration will be active. See the BAM chapter in the RM. It also depends on your boot mode. It is possible the default config allows you to access.

4. Then that might be the problem since in the AIPS_PACRn registers, you have set all SPx bits to 1, meaning only Supervisor accesses are allowed. You need to put this bit to 0 for each slave to allow User accesses to them.

Étienne

Re: AIPS & MPU in MPC5777C

yashkumar — Tue, 17 Jul 2018 16:51:33 GMT

Hi Etienne,
1.Yes i need to correct that,this was due to copy/paste,that would be:
/* For STACK of (XBAR Slave Port 4 )*/
MPU1.RGD[2].WORD0.R = 0x40040400; /* Start address */
MPU1.RGD[2].WORD1.R = 0x40040FFF; /* End address */

2.Yes, i will read the BAM chapter.

3.yes, i had tried this way as well, i means to say:
AIPS0_MPRA = 0x70000000;
AIPS0_MPRB = 0x50000000;
AIPS0_PACRA =0x00000000;
AIPS0_PACRB =0x00000000;

(PACR[0] =5: due to just modifying AIPS_0 in supervisor mode, and not accessible AIPS_0 registers in user mode )
But, still i was getting memory fault during access the STM register.

My main concern is here that, if i have covered the Peripheral Bridge A & B with MPU0.RGD[1] and MPU1.RGD[1]repectively with PID 0xFF, which is for supervisor access during running of TRUSTED Application.

Does i can allow the Peripheral Register by using AIPS0 and AIPS1, for NON-TRUSTED Applications which has PID 0x01.

As For NON-TRUSTED Application no memory block configured for Peripheral Register,

i want give access, after checking if these non-trusted application have Peripheral Access TRUE. Then provide access by APIS0/APIS1,without configuring any memory block for Peripheral Bridge A & B.

Thanks!

Re: AIPS & MPU in MPC5777C

yashkumar — Fri, 20 Jul 2018 18:01:50 GMT

Hi,

I read ,BAM .I nothing found deference to access permission .

what is role Guarded bit .

could please look in above question.

Thanks!

Re: AIPS & MPU in MPC5777C

EAlepins — Mon, 23 Jul 2018 22:10:02 GMT

Guarded means that speculative reads will not occur. It is a good idea to put guarded peripheral registers. However, it is better for performacne to put RAM not guarded.

To help you find the cause of the exception, let's take it the opposite way: from the exception itself. Are you using an RTOS that gives you a diagnostic of the type of memory fault? If not, then as soon as you have the exception, record the following:

- Which IVOR vector was triggered? (IVOR1 Machine Check? IVOR2 Data Storage?)

- If Machine Check, then save MCSR core register value. If Data Storage, save ESR.

- Save MPU0/1 CESR, EARn, EDRn where "n" is CESR[SPERR]: if your problem is an MPU fault, it will give you details (make sure all these registers were zero before your test)

Re: AIPS & MPU in MPC5777C

yashkumar — Wed, 25 Jul 2018 15:27:26 GMT

Hi,

Thanks for response.

It is hitting to IVOR1 FAULT .

how i can allow the Peripheral Register by using AIPS0 and AIPS1, for NON-TRUSTED Applications which has PID 0x01.

This NON-TRUSTED Application has no memory block configured for Peripheral Register.

Now, i want give access, after checking if these non-trusted application have Peripheral Access TRUE.

Then provide access by APIS0/APIS1,without configuring any memory block for Peripheral Bridge A & B.

Thanks!

Re: AIPS & MPU in MPC5777C

EAlepins — Mon, 30 Jul 2018 15:35:25 GMT

I don't clearly understand. But in order to identify the cause of the exception, please post the value of the following register before your access + after your access:

MPU0 & 1 CESR, EARn, EDRn (where "n" is CESR[SPERR])

Re: AIPS & MPU in MPC5777C

yashkumar — Mon, 30 Jul 2018 16:12:26 GMT

This is not my problem. I know that cause of error.

I am accessing the peripheral register for an application, which has no access permission provided.

That’s why I am getting memory fault (IVOR1 Machine Check).

So, here my question is how I can provide access to that peripheral register.

I have already given the implementation in above post using APIS0/APIS1,without configuring any memory block for Peripheral Bridge A & B., but still getting memory fault.

Re: AIPS & MPU in MPC5777C

EAlepins — Mon, 30 Jul 2018 19:19:32 GMT

I was asking that question to try to understand who between Core MMU, MPU and AIPS was generating the access fault.

Just trying to summarize: both APP_0 and APP_1 are running on core 0. Also, between APP_0 and APP_1 execution, you are not changing any of the following: core0 MMU configuration, MPU0+1 configuration, AIPS/PBRIDGE configuration. Right?

Your goal is that APP_1 be able to read/write to STM registers (which are inside PBRIDGE_B memory map). Right?

You are able to read/write to those STM registers in APP_0, right?

- If so, I don't understand why you call APP_0 "trusted" and APP_1 "untrusted" since there the "trust" concept only exists in AIPS and there is no register defined in AIPS to differentiate when APP_0 or APP_1 is running.

- By the way, are you changing the value of the PID0 core register (SPR 48) when switching between APP_0 and APP_1? That's the register used to tell the MPU which PID is running.

- Is APP_0 running in User or Supervisor mode?

I don't quite understand: if you want APP_1 to be able to access STM registers, the Core MMU, MPU1 and AIPS will need to allow User mode access. So you'll need entries in MPU1 for that. You'll need, while APP_1 is running:

/* Peripheral Bridge B Registers */
MPU1.RGD[0].WORD0.R = 0xFFE00000; /* Start address */
MPU1.RGD[0].WORD1.R = 0xFFFFFFFF; /* End address */
MPU1.RGD[0].WORD2.R = 0x0000001F; /* Read-write-execute allowed for all master */
MPU1.RGD[0].WORD3.R = 0x00000001; /* Mark descriptor as valid */

AIPS0_MPRA = 0x70000000;

AIPS0_MPRB = 0x00000000;

AIPS0_PACRA =0x00000000;

AIPS0_PACRB =0x00000000;

I think your problem was that MPU1[0] was only giving STM access to PID=0xFF (APP_0). You have to disable PID-check for that MPU region.