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    <title>MPC5xxxのトピックRe: SRAM ECC Algorithm for MPC56xx</title>
    <link>https://community.nxp.com/t5/MPC5xxx/SRAM-ECC-Algorithm-for-MPC56xx/m-p/770506#M11069</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;Is ECC algorithm for SRAM , applied to whole memory region or just dedicated memory space for this test.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;1. ECC mechanism is used on whole SRAM.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;If they are applied to whole memory, how to manage data changes in SRAM? Variable changes are written with their new error bits?&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;2. On every write there is a new syndrome written along with data.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;If I change an area in SRAM during debug session, this change isn't perceived as ECC error by the microcontroller, Why? Especially, I need&amp;nbsp;to know that, &lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;3. Debugger write to SRAM via SRAM controller where the ECC syndrome is generated and stored in SRAM array.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;If there is one or more bit change(caused by radiation, electro-magnetic interference, or electrical noise) in any region of SRAM,&amp;nbsp;will ecc detect this error?&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;4. Yes, ECC mechanism will detect that stored data+syndrome are different from the one read by controller. This is how the ECC works in general.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;In generally, how does ECC work?&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;5.Would be good to read for example AN where it is already explained or some general documentation like reference manual.&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/application-note/AN5200.pdf?fsrch=1&amp;amp;sr=1&amp;amp;pageNum=1" title="https://www.nxp.com/docs/en/application-note/AN5200.pdf?fsrch=1&amp;amp;sr=1&amp;amp;pageNum=1"&gt;https://www.nxp.com/docs/en/application-note/AN5200.pdf?fsrch=1&amp;amp;sr=1&amp;amp;pageNum=1&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 21 Mar 2018 06:52:13 GMT</pubDate>
    <dc:creator>petervlna</dc:creator>
    <dc:date>2018-03-21T06:52:13Z</dc:date>
    <item>
      <title>SRAM ECC Algorithm for MPC56xx</title>
      <link>https://community.nxp.com/t5/MPC5xxx/SRAM-ECC-Algorithm-for-MPC56xx/m-p/770505#M11068</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV class="" style="height: 401px;"&gt;&lt;DIV class=""&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR class=""&gt;&lt;TD class=""&gt;&lt;DIV&gt;Is ECC algorithm for SRAM , applied to whole memory region or just dedicated memory space for this test.&lt;BR /&gt;If they are applied to whole memory, how to manage data changes in SRAM? Variable changes are written with their new error bits? &lt;BR /&gt;If I change an area in SRAM during debug session, this change isn't perceived as ECC error by the microcontroller, Why? Especially, I need&amp;nbsp;to know that, If there is one or more bit change(caused by radiation, electro-magnetic interference, or electrical noise) in any region of SRAM,&amp;nbsp;will ecc detect this error?&lt;/DIV&gt;&lt;DIV&gt; &lt;/DIV&gt;&lt;DIV&gt;In generally, how does ECC work?&lt;/DIV&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 19 Mar 2018 11:04:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/SRAM-ECC-Algorithm-for-MPC56xx/m-p/770505#M11068</guid>
      <dc:creator>kadiraktas</dc:creator>
      <dc:date>2018-03-19T11:04:07Z</dc:date>
    </item>
    <item>
      <title>Re: SRAM ECC Algorithm for MPC56xx</title>
      <link>https://community.nxp.com/t5/MPC5xxx/SRAM-ECC-Algorithm-for-MPC56xx/m-p/770506#M11069</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;Is ECC algorithm for SRAM , applied to whole memory region or just dedicated memory space for this test.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;1. ECC mechanism is used on whole SRAM.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;If they are applied to whole memory, how to manage data changes in SRAM? Variable changes are written with their new error bits?&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;2. On every write there is a new syndrome written along with data.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;If I change an area in SRAM during debug session, this change isn't perceived as ECC error by the microcontroller, Why? Especially, I need&amp;nbsp;to know that, &lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;3. Debugger write to SRAM via SRAM controller where the ECC syndrome is generated and stored in SRAM array.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;If there is one or more bit change(caused by radiation, electro-magnetic interference, or electrical noise) in any region of SRAM,&amp;nbsp;will ecc detect this error?&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;4. Yes, ECC mechanism will detect that stored data+syndrome are different from the one read by controller. This is how the ECC works in general.&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;In generally, how does ECC work?&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;5.Would be good to read for example AN where it is already explained or some general documentation like reference manual.&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/application-note/AN5200.pdf?fsrch=1&amp;amp;sr=1&amp;amp;pageNum=1" title="https://www.nxp.com/docs/en/application-note/AN5200.pdf?fsrch=1&amp;amp;sr=1&amp;amp;pageNum=1"&gt;https://www.nxp.com/docs/en/application-note/AN5200.pdf?fsrch=1&amp;amp;sr=1&amp;amp;pageNum=1&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 21 Mar 2018 06:52:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MPC5xxx/SRAM-ECC-Algorithm-for-MPC56xx/m-p/770506#M11069</guid>
      <dc:creator>petervlna</dc:creator>
      <dc:date>2018-03-21T06:52:13Z</dc:date>
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