topic Re: Hall Sensor XOR in Motor Control and Smart Energy

Hall Sensor XOR

ewilliams — Thu, 19 Sep 2019 16:27:13 GMT

Hello,

In the KV31F sub-family reference manual, there's a handy note regarding using the two 2-CH FTM modules (FTM1 and FTM2) in input capture mode for hall sensor decoding. Apparently one of the SIM_SOPT4 register bits controls the input to FTM2 CH1. If the three hall sensors are connected to FTM1 CH0, FTM1 CH1, and FTM2 CH0 then setting this bit appropriately will result in the "Exclusive-OR" of the three hall sensor lines which could result in reduced complexity in calculation.

My question is regarding the interpretation of "Exclusive OR" for 3 signals, as there are typically two interpretations. Is this an "Only 1" (xor output is true only if only one input is true) or an "odd parity" (xor output is true if an odd number of inputs are true) interpretation?

Thanks,

Eric

Re: Hall Sensor XOR

Robin_Shen — Fri, 20 Sep 2019 06:39:29 GMT

Hi Eric,

I think it's an "odd parity" (xor output is true if an odd number of inputs are true). You can have a try to test it.

Best Regards,

Robin

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Re: Hall Sensor XOR

pandi — Thu, 25 Apr 2024 10:03:17 GMT

@ewilliams

We are using KV31 Hall_XOR how to hall sensor signals read in FTM1,FTM2 reference manual

based we are configured and that is not proper working in our configuration code bellow if any changes and missing registers

void InitFTM1(void)

{

/* enable clock to FTM module */

// SIM->SCGC6 |= SIM_SCGC6_FTM1_MASK;

FTM1->MODE = FTM_MODE_WPDIS_MASK | FTM_MODE_FTMEN_MASK;

FTM1->SC = FTM_SC_PS(4) | FTM_SC_CLKS(1) | FTM_SC_TOIE_MASK;

FTM1->CONF = FTM_CONF_BDMMODE(3);

FTM1->MOD = 0xFFFF;

FTM1->CNTIN = 0x0;

FTM1->CONTROLS[1].CnSC |= FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK;

FTM1->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;

EnableIRQ(FTM1_IRQn);

}

void InitFTM2(void)

{

SIM->SCGC6 |= SIM_SCGC6_FTM2_MASK|SIM_SCGC6_FTM1_MASK;

SIM->SOPT4 |= SIM_SOPT4_FTM2CH1SRC_MASK;

FTM2->MODE |= FTM_MODE_FTMEN_MASK;

FTM2->CONF |= FTM_CONF_BDMMODE(3);

FTM2->MOD = 0xFFFF;

FTM2->CNTIN = 0;

FTM2->SC |= FTM_SC_CLKS(1);

FTM2->SC |= FTM_SC_PS(7);

FTM2->CONTROLS[0].CnSC |= FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK;

FTM2->CONTROLS[1].CnSC |= FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK | FTM_CnSC_ICRST_MASK;

FTM2->CONTROLS[1].CnSC |= FTM_CnSC_CHIE_MASK;

EnableIRQ(FTM2_IRQn);

}

PANDI