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    <title>MCUXpresso SDK中的主题 Two continuous LPSPI blocking transfer</title>
    <link>https://community.nxp.com/t5/MCUXpresso-SDK/Two-continuous-LPSPI-blocking-transfer/m-p/1851685#M4724</link>
    <description>&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;I have to read data from a serial Nor flash, connected to my RT1xxx through LPSPIx.&lt;/P&gt;&lt;P&gt;I have to send one command byte and then I have to read 10KB data.&lt;/P&gt;&lt;P&gt;It would be nice to do this with two transfers:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;a 5-byte transfer in tx, composed by&lt;BR /&gt;1 command byte&lt;BR /&gt;3 address byte&lt;BR /&gt;1 dummy byte&lt;/LI&gt;&lt;LI&gt;another transfer with 10KB rx buffer, and NULL tx buffer&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;obviously the chip-select must be asserted at the first transfer and de-asserted at the end of the second transfer, between the two transfers the chip-select must remain asserted. In other words CONT must be 1 and CONTC 0 in the first transfer. While in the second transfer both CONT and CONTC must be 1. At the end of the second transfer CONTC shoud be written 0 to deassert CS. Obviously only one TCR write must be made between the two transactions.&lt;/P&gt;&lt;P&gt;I tried to draw a time diagram to explain myself better:&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="wavedrom.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/275042i3E93138C752FC1EF/image-size/large?v=v2&amp;amp;px=999" role="button" title="wavedrom.png" alt="wavedrom.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;wavedrom.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;In the first transaction I only write, in the second transaction I only read, but between the two the PCS &lt;U&gt;&lt;STRONG&gt;must&lt;/STRONG&gt;&lt;/U&gt; remain asserted.&lt;/P&gt;&lt;P&gt;I am using SDK 2.15.000, how can I achieve this behavior using API of SDK?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;You may ask why do I need this? A single call to LPSPI_MasterTransferBlocking() would force me to allocate both rxData and txData buffers with two vectors of more than 10KB, in which the tx buffer is completely useless. Is exactly what I would like to avoid.&lt;/P&gt;&lt;P&gt;Note that some years ago I asked &lt;A href="https://community.nxp.com/t5/i-MX-RT/Two-continuous-LPSPI-blocking-transfer/m-p/883420" target="_blank" rel="noopener"&gt;the same question&lt;/A&gt;, but did not get a satisfactory answer.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;best regards&lt;/P&gt;&lt;P&gt;Max&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Mon, 22 Apr 2024 13:55:37 GMT</pubDate>
    <dc:creator>mastupristi</dc:creator>
    <dc:date>2024-04-22T13:55:37Z</dc:date>
    <item>
      <title>Two continuous LPSPI blocking transfer</title>
      <link>https://community.nxp.com/t5/MCUXpresso-SDK/Two-continuous-LPSPI-blocking-transfer/m-p/1851685#M4724</link>
      <description>&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;P&gt;I have to read data from a serial Nor flash, connected to my RT1xxx through LPSPIx.&lt;/P&gt;&lt;P&gt;I have to send one command byte and then I have to read 10KB data.&lt;/P&gt;&lt;P&gt;It would be nice to do this with two transfers:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;a 5-byte transfer in tx, composed by&lt;BR /&gt;1 command byte&lt;BR /&gt;3 address byte&lt;BR /&gt;1 dummy byte&lt;/LI&gt;&lt;LI&gt;another transfer with 10KB rx buffer, and NULL tx buffer&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;obviously the chip-select must be asserted at the first transfer and de-asserted at the end of the second transfer, between the two transfers the chip-select must remain asserted. In other words CONT must be 1 and CONTC 0 in the first transfer. While in the second transfer both CONT and CONTC must be 1. At the end of the second transfer CONTC shoud be written 0 to deassert CS. Obviously only one TCR write must be made between the two transactions.&lt;/P&gt;&lt;P&gt;I tried to draw a time diagram to explain myself better:&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="wavedrom.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/275042i3E93138C752FC1EF/image-size/large?v=v2&amp;amp;px=999" role="button" title="wavedrom.png" alt="wavedrom.png" /&gt;&lt;span class="lia-inline-image-caption" onclick="event.preventDefault();"&gt;wavedrom.png&lt;/span&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;In the first transaction I only write, in the second transaction I only read, but between the two the PCS &lt;U&gt;&lt;STRONG&gt;must&lt;/STRONG&gt;&lt;/U&gt; remain asserted.&lt;/P&gt;&lt;P&gt;I am using SDK 2.15.000, how can I achieve this behavior using API of SDK?&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;You may ask why do I need this? A single call to LPSPI_MasterTransferBlocking() would force me to allocate both rxData and txData buffers with two vectors of more than 10KB, in which the tx buffer is completely useless. Is exactly what I would like to avoid.&lt;/P&gt;&lt;P&gt;Note that some years ago I asked &lt;A href="https://community.nxp.com/t5/i-MX-RT/Two-continuous-LPSPI-blocking-transfer/m-p/883420" target="_blank" rel="noopener"&gt;the same question&lt;/A&gt;, but did not get a satisfactory answer.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;best regards&lt;/P&gt;&lt;P&gt;Max&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 22 Apr 2024 13:55:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCUXpresso-SDK/Two-continuous-LPSPI-blocking-transfer/m-p/1851685#M4724</guid>
      <dc:creator>mastupristi</dc:creator>
      <dc:date>2024-04-22T13:55:37Z</dc:date>
    </item>
    <item>
      <title>Re: Two continuous LPSPI blocking transfer</title>
      <link>https://community.nxp.com/t5/MCUXpresso-SDK/Two-continuous-LPSPI-blocking-transfer/m-p/1858588#M4744</link>
      <description>&lt;P&gt;Hello&lt;/P&gt;
&lt;P&gt;I agree with the previous response, I suggest you use LPSPI_MasterTransferNonBlocking() since it has a handle that allows you to configure the bytes to receive/transmit.&lt;/P&gt;
&lt;P&gt;In continuous mode, there are some known issues so you can opt to use PCS as GPIO to have control on it. Details on this issue are found here: &lt;A href="https://community.nxp.com/t5/i-MX-RT/RT1050-LPSPI-last-bit-not-completing-in-continuous-mode/m-p/898460" target="_blank"&gt;Solved: RT1050 LPSPI last bit not completing in continuous mode - NXP Community&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;BR /&gt;Omar&lt;/P&gt;</description>
      <pubDate>Thu, 02 May 2024 20:00:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/MCUXpresso-SDK/Two-continuous-LPSPI-blocking-transfer/m-p/1858588#M4744</guid>
      <dc:creator>Omar_Anguiano</dc:creator>
      <dc:date>2024-05-02T20:00:50Z</dc:date>
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