topic Re: FLEXSPI NOR POLLING Modification and Questions in MCUXpresso SDK

FLEXSPI NOR POLLING Modification and Questions

chadgraham — Wed, 21 Jul 2021 14:26:13 GMT

Hello,

I am trying to modify the FLEXSPI example to work with a second QSPI chip, but I'm running into some issues and I have some fundamental questions regarding the example.

Background:

I am working with the RT1060 dev board and the 2.9.3 SDK in MCUXpresso 11.3.1. On the dev board, we have attached a second IS25WP064A and connected the chip select signal to [P2] GPIO_SD_B1_04. In software, I have added the chip select signal to the FLEXSPI group, labeled it as FlexSPI_SS1, and configured it the same way as FlexSPI_SS0 (IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B, 0x10F1U);). Additionally, I have modified flexspi_nor_config_t qspiflash_config in evkmimrt1060_flexspi_nor_config.c and added .sflashA2Size = 8u * 1024u * 1024u.

Problem:

I am unable to confirm that the second QSPI chip is responding and is being controlled.

Questions:

When the programmer takes control and starts to program the board, the MIMXRT1060_SFDP_QSPI.cfx detects two chips, but they are the same address (0x60000000). Is this expected or is this the first sign that something isn't correct.
Since this is XIP, does the memory viewer not allow me to change the memory directly?
Is it expected that the A2 chip memory location has the same data as the A1 chip for the header location?
Looking at the code, I can see that it initializes A1 directly. Do I need to initialize A2 in the same way?

I will upload the project I am working with shortly.

Re: FLEXSPI NOR POLLING Modification and Questions

chadgraham — Wed, 21 Jul 2021 14:22:59 GMT

Re: FLEXSPI NOR POLLING Modification and Questions

FelipeGarcia — Fri, 23 Jul 2021 18:15:00 GMT

Hi,

As you are using FlexSPI A1 and A2 memory should be located in different locations. Please check image below. When using parallel mode, FlexSPI will merge/split the flash read/program data automatically and behave as one memory.

So you will use the two QSPI for XIP? If that is the case and you are not using parallel mode a problem can occur when there is a code instruction placed on the address border between each memory. I think parallel mode is more accurate to your application.

Please see my answer 1.

Yes.

Best regards,

Felipe

Re: FLEXSPI NOR POLLING Modification and Questions

chadgraham — Mon, 26 Jul 2021 12:49:18 GMT

Hello Felipe,

My understanding is that the parallel mode will split the data and commands between two devices, one on port A and one on port B. Does parallel mode also work with two devices on the same port?
Yes, I want to use both parts as a single XIP memory space.
Ok
Do both chips get the same config data or will one be slightly different?

Re: FLEXSPI NOR POLLING Modification and Questions

FelipeGarcia — Wed, 28 Jul 2021 20:54:52 GMT

Hi,

In parallel mode, A1 and A2 could not be accessed at the same time. Same for B1 and B2. Please refer to Chapter 9.6.3.1 for boot Configuration, and the "Bit2 – ParallelModeEnable" of "controllerMiscOption" register for parallel mode enable.

Best regards,

Felipe

Re: FLEXSPI NOR POLLING Modification and Questions

chadgraham — Fri, 06 Aug 2021 12:38:33 GMT

Hello,

After much hardship, I was able to get this to work. In case other people are interested, I posted a working version of the example code at FlexSPI A2 Chip Select Not Toggling.