Deterministic Sub-Microsecond Safety Layer for Edge AI on Cortex-M (1.18 µs Latency)

kretski — Sat, 04 Apr 2026 01:01:17 GMT

Hi everyone,

I wanted to share a project designed for mission-critical Edge AI on resource-constrained MCUs like the STM32, LPC, and i.MX series.

MicroSafe-RL is a deterministic C++ safety interceptor that sits between an AI agent and the hardware actuators. It prevents unsafe commands from damaging hardware during Reinforcement Learning exploration or due to sensor drift.

Technical Highlights:

Latency: 1.18 microseconds (WCET) on Cortex-M3 at 72MHz.

Memory: Exactly 20 bytes of RAM, zero dynamic allocation (malloc-free).

Logic: O(1) deterministic execution.

Safety: Uses EMA and MAD statistical profiling to detect hardware drift in real-time.

The project methodology is currently under review at IEEE Transactions on Aerospace and Electronic Systems (Manuscript ID: TAES-2026-1001).

I am looking for feedback from the community on further MISRA-C compliance and hardware-specific optimizations.

GitHub: https://github.com/Kretski/MicroSafe-RL
Zenodo DOI: 10.5281/zenodo.19019599

topic Deterministic Sub-Microsecond Safety Layer for Edge AI on Cortex-M (1.18 µs Latency) in MCUXpresso General

Deterministic Sub-Microsecond Safety Layer for Edge AI on Cortex-M (1.18 µs Latency)