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    <title>topic CMU registers in Model-Based Design Toolbox (MBDT)</title>
    <link>https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/CMU-registers/m-p/1378240#M6754</link>
    <description>&lt;P&gt;On writing 0 to the&amp;nbsp;SELCTL (7th bit) to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;MC_CGM_AC3_SC&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;amp;&amp;nbsp;&lt;STRONG&gt;MC_CGM_AC4_SC&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;registers, Freemaster doesn't see the board COM port&amp;nbsp;&lt;/P&gt;&lt;P&gt;On writing 1 to&amp;nbsp;On writing 0 to the&amp;nbsp;SELCTL (7th bit) to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;MC_CGM_AC3_SC&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and&amp;nbsp;&lt;STRONG&gt;MC_CGM_AC4_SC&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;register to choose the&amp;nbsp;&amp;nbsp;8-40 MHz XOSC as a clock source, I don't get the desired output in the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;MC_ME_GS&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;register in the S_SYSCLK (28–31) bits, that I expect to be 0001 (4-40 MHz XOSC)&lt;/P&gt;</description>
    <pubDate>Mon, 29 Nov 2021 13:38:23 GMT</pubDate>
    <dc:creator>Amr_Awny</dc:creator>
    <dc:date>2021-11-29T13:38:23Z</dc:date>
    <item>
      <title>CMU registers</title>
      <link>https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/CMU-registers/m-p/1378240#M6754</link>
      <description>&lt;P&gt;On writing 0 to the&amp;nbsp;SELCTL (7th bit) to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;MC_CGM_AC3_SC&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&amp;amp;&amp;nbsp;&lt;STRONG&gt;MC_CGM_AC4_SC&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;registers, Freemaster doesn't see the board COM port&amp;nbsp;&lt;/P&gt;&lt;P&gt;On writing 1 to&amp;nbsp;On writing 0 to the&amp;nbsp;SELCTL (7th bit) to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;MC_CGM_AC3_SC&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and&amp;nbsp;&lt;STRONG&gt;MC_CGM_AC4_SC&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;register to choose the&amp;nbsp;&amp;nbsp;8-40 MHz XOSC as a clock source, I don't get the desired output in the&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;MC_ME_GS&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;register in the S_SYSCLK (28–31) bits, that I expect to be 0001 (4-40 MHz XOSC)&lt;/P&gt;</description>
      <pubDate>Mon, 29 Nov 2021 13:38:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/CMU-registers/m-p/1378240#M6754</guid>
      <dc:creator>Amr_Awny</dc:creator>
      <dc:date>2021-11-29T13:38:23Z</dc:date>
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