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    <title>topic Unable to Read Registers of MSDI chip CD1030 over SPI on MPC5775B EVB in Model-Based Design Toolbox (MBDT)</title>
    <link>https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/Unable-to-Read-Registers-of-MSDI-chip-CD1030-over-SPI-on/m-p/1202424#M5513</link>
    <description>&lt;P&gt;We are creating an example model using the NXP&amp;nbsp;Model-Based Design Toolbox (MBDT)&amp;nbsp;&lt;SPAN&gt;Version &lt;/SPAN&gt;&lt;SPAN class="ls1"&gt;3.&lt;/SPAN&gt;&lt;SPAN&gt;2&lt;/SPAN&gt;&lt;SPAN class="ls2"&gt;.0&lt;/SPAN&gt; for&amp;nbsp;MPC57xx Series processors to create an example interfacing with the&amp;nbsp;MSDI chip CD1030 over SPI bus from the MPC5777C processor, see the attached model.&amp;nbsp;&lt;/P&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;We are able to send the 32-bit "SPI Check" message [0x00 0x00 0x00 0x00] as uint8(4) and get the expected response 0x00123456 from the "SPI Master Transfer" block.&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;However, when we try to read the switch status SP or SG registers using messages&amp;nbsp;[ 0x3C 0x00 0x00 0x00 ] and&amp;nbsp;[ 0x3E 0x00 0x00 0x00 ] respectively, we a response 0x3f&lt;STRONG&gt;badbad&lt;/STRONG&gt;. Seeing "bad" plainly visible repeated twice in the response (as Hexspeak) suggests something is terribly wrong.&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dspi_test_mpc577c_MSDI_minimal_query.png" style="width: 522px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133174iB8224EC7A06E3612/image-dimensions/522x282?v=v2" width="522" height="282" role="button" title="dspi_test_mpc577c_MSDI_minimal_query.png" alt="dspi_test_mpc577c_MSDI_minimal_query.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;By comparison, the response from the SPI Check message is as expected:&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dspi_test_mpc577c_MSDI_minimal_SPI-test.png" style="width: 523px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133175iECDE5BF36FF80FFB/image-dimensions/523x283?v=v2" width="523" height="283" role="button" title="dspi_test_mpc577c_MSDI_minimal_SPI-test.png" alt="dspi_test_mpc577c_MSDI_minimal_SPI-test.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;The simplified top-level model:&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dspi_test_mpc577c_MSDI_system.png" style="width: 470px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133176iC1E565BFD13F5BEE/image-dimensions/470x360?v=v2" width="470" height="360" role="button" title="dspi_test_mpc577c_MSDI_system.png" alt="dspi_test_mpc577c_MSDI_system.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;And the state chart that passes messages to the&amp;nbsp;CD1030&amp;nbsp;MSDI chip:&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dspi_test_mpc577c_MSDI_minimal_chart.png" style="width: 880px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133177i511C876C5FDCA4C8/image-size/large?v=v2&amp;amp;px=999" role="button" title="dspi_test_mpc577c_MSDI_minimal_chart.png" alt="dspi_test_mpc577c_MSDI_minimal_chart.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;The SPI Config Block used Continuous Transfer and Frame Size 8:&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dspi_test_mpc577c_MSDI_minimal_spi-config.png" style="width: 486px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133178i3716E82125B83D92/image-dimensions/486x289?v=v2" width="486" height="289" role="button" title="dspi_test_mpc577c_MSDI_minimal_spi-config.png" alt="dspi_test_mpc577c_MSDI_minimal_spi-config.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;The above configuration was set based on an answer to a previous question:&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;Request for HSD/LSD/MSDI Communication Examples for MPC5775B BMS and VCU Reference Design&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;A title="Request for HSD/LSD/MSDI Communication Examples for MPC5775B BMS and VCU Reference Design" href="https://community.nxp.com/t5/NXP-Model-Based-Design-Tools/Request-for-HSD-LSD-MSDI-Communication-Examples-for-MPC5775B-BMS/m-p/1195140#M5466" target="_self"&gt;https://community.nxp.com/t5/NXP-Model-Based-Design-Tools/Request-for-HSD-LSD-MSDI-Communication-Examples-for-MPC5775B-BMS/m-p/1195140#M5466&lt;/A&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;The above was extremely helpful, but going forward brings us to a new challenge.&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;Further guidance would be greatly appreciated.&amp;nbsp; Thanks.&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;</description>
    <pubDate>Mon, 21 Dec 2020 10:07:05 GMT</pubDate>
    <dc:creator>rsating</dc:creator>
    <dc:date>2020-12-21T10:07:05Z</dc:date>
    <item>
      <title>Unable to Read Registers of MSDI chip CD1030 over SPI on MPC5775B EVB</title>
      <link>https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/Unable-to-Read-Registers-of-MSDI-chip-CD1030-over-SPI-on/m-p/1202424#M5513</link>
      <description>&lt;P&gt;We are creating an example model using the NXP&amp;nbsp;Model-Based Design Toolbox (MBDT)&amp;nbsp;&lt;SPAN&gt;Version &lt;/SPAN&gt;&lt;SPAN class="ls1"&gt;3.&lt;/SPAN&gt;&lt;SPAN&gt;2&lt;/SPAN&gt;&lt;SPAN class="ls2"&gt;.0&lt;/SPAN&gt; for&amp;nbsp;MPC57xx Series processors to create an example interfacing with the&amp;nbsp;MSDI chip CD1030 over SPI bus from the MPC5777C processor, see the attached model.&amp;nbsp;&lt;/P&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;We are able to send the 32-bit "SPI Check" message [0x00 0x00 0x00 0x00] as uint8(4) and get the expected response 0x00123456 from the "SPI Master Transfer" block.&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;However, when we try to read the switch status SP or SG registers using messages&amp;nbsp;[ 0x3C 0x00 0x00 0x00 ] and&amp;nbsp;[ 0x3E 0x00 0x00 0x00 ] respectively, we a response 0x3f&lt;STRONG&gt;badbad&lt;/STRONG&gt;. Seeing "bad" plainly visible repeated twice in the response (as Hexspeak) suggests something is terribly wrong.&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dspi_test_mpc577c_MSDI_minimal_query.png" style="width: 522px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133174iB8224EC7A06E3612/image-dimensions/522x282?v=v2" width="522" height="282" role="button" title="dspi_test_mpc577c_MSDI_minimal_query.png" alt="dspi_test_mpc577c_MSDI_minimal_query.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;By comparison, the response from the SPI Check message is as expected:&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dspi_test_mpc577c_MSDI_minimal_SPI-test.png" style="width: 523px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133175iECDE5BF36FF80FFB/image-dimensions/523x283?v=v2" width="523" height="283" role="button" title="dspi_test_mpc577c_MSDI_minimal_SPI-test.png" alt="dspi_test_mpc577c_MSDI_minimal_SPI-test.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;The simplified top-level model:&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dspi_test_mpc577c_MSDI_system.png" style="width: 470px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133176iC1E565BFD13F5BEE/image-dimensions/470x360?v=v2" width="470" height="360" role="button" title="dspi_test_mpc577c_MSDI_system.png" alt="dspi_test_mpc577c_MSDI_system.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;And the state chart that passes messages to the&amp;nbsp;CD1030&amp;nbsp;MSDI chip:&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dspi_test_mpc577c_MSDI_minimal_chart.png" style="width: 880px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133177i511C876C5FDCA4C8/image-size/large?v=v2&amp;amp;px=999" role="button" title="dspi_test_mpc577c_MSDI_minimal_chart.png" alt="dspi_test_mpc577c_MSDI_minimal_chart.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;The SPI Config Block used Continuous Transfer and Frame Size 8:&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dspi_test_mpc577c_MSDI_minimal_spi-config.png" style="width: 486px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133178i3716E82125B83D92/image-dimensions/486x289?v=v2" width="486" height="289" role="button" title="dspi_test_mpc577c_MSDI_minimal_spi-config.png" alt="dspi_test_mpc577c_MSDI_minimal_spi-config.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;The above configuration was set based on an answer to a previous question:&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;Request for HSD/LSD/MSDI Communication Examples for MPC5775B BMS and VCU Reference Design&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0 lia-indent-padding-left-30px"&gt;&lt;A title="Request for HSD/LSD/MSDI Communication Examples for MPC5775B BMS and VCU Reference Design" href="https://community.nxp.com/t5/NXP-Model-Based-Design-Tools/Request-for-HSD-LSD-MSDI-Communication-Examples-for-MPC5775B-BMS/m-p/1195140#M5466" target="_self"&gt;https://community.nxp.com/t5/NXP-Model-Based-Design-Tools/Request-for-HSD-LSD-MSDI-Communication-Examples-for-MPC5775B-BMS/m-p/1195140#M5466&lt;/A&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;The above was extremely helpful, but going forward brings us to a new challenge.&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;Further guidance would be greatly appreciated.&amp;nbsp; Thanks.&lt;/DIV&gt;&lt;DIV class="t m0 x1 h5 yd ff1 fs3 fc0 sc0 ls0 ws0"&gt;&amp;nbsp;&lt;/DIV&gt;</description>
      <pubDate>Mon, 21 Dec 2020 10:07:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/Unable-to-Read-Registers-of-MSDI-chip-CD1030-over-SPI-on/m-p/1202424#M5513</guid>
      <dc:creator>rsating</dc:creator>
      <dc:date>2020-12-21T10:07:05Z</dc:date>
    </item>
    <item>
      <title>Re: Unable to Read Registers of MSDI chip CD1030 over SPI on MPC5775B EVB</title>
      <link>https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/Unable-to-Read-Registers-of-MSDI-chip-CD1030-over-SPI-on/m-p/1203695#M5529</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/178673"&gt;@rsating&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;Unfortunately, I don't have access to the CD1030 so it is very hard to help you with this.&lt;/P&gt;
&lt;P&gt;Since you still get something from the CD1030 I think the communication settings are fine so this is most likely a register logic issue. Maybe there are some initialization commands that have to be sent before accessing those registers.&lt;/P&gt;
&lt;P&gt;On this page I've found an Interface Software Driving for Multiple Switch Detection which may help you with some extra information.&amp;nbsp;&lt;A href="https://www.nxp.com/products/interfaces/signal-conditioners/33-channel-multiple-switch-detection-interface-with-programmable-current:CD1030?tab=Design_Tools_Tab" target="_blank"&gt;https://www.nxp.com/products/interfaces/signal-conditioners/33-channel-multiple-switch-detection-interface-with-programmable-current:CD1030?tab=Design_Tools_Tab&lt;/A&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="mariuslucianand_0-1608731169794.png" style="width: 999px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/133424iBC0849CA19271F98/image-size/large?v=v2&amp;amp;px=999" role="button" title="mariuslucianand_0-1608731169794.png" alt="mariuslucianand_0-1608731169794.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Another interesting aspect that may be taken into account is the possibility of integrating custom code. For example, the driver above can be integrated into your MBDT project in a similar way described here&amp;nbsp;&lt;A href="https://community.nxp.com/t5/NXP-Model-Based-Design-Tools/How-to-use-your-own-C-code-in-our-Toolbox-Battery-Management/ta-p/1119004" target="_blank"&gt;https://community.nxp.com/t5/NXP-Model-Based-Design-Tools/How-to-use-your-own-C-code-in-our-Toolbox-Battery-Management/ta-p/1119004&amp;nbsp;&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Of course, there are some extra steps required like: You have to implement wrappers over some functions from the Driver which can be directly called by an S-Function. You have to write yourself the&lt;SPAN style="font-family: inherit;"&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-family: inherit;"&gt;MSDI_TransferSpi function to access the SPI driver used in the MBDT function but you already have an example in the archive that contains the MSDI Driver. This is for S32K but the SPI driver looks very much with the one used by the MPC&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;At least you can have a look at the commands sent by the driver to see if there are some other registers written in the initialization. Or how the registers you are interested in can be accessed.&lt;/P&gt;
&lt;P&gt;Hope this helps,&lt;/P&gt;
&lt;P&gt;Marius&lt;/P&gt;</description>
      <pubDate>Wed, 23 Dec 2020 13:53:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Model-Based-Design-Toolbox-MBDT/Unable-to-Read-Registers-of-MSDI-chip-CD1030-over-SPI-on/m-p/1203695#M5529</guid>
      <dc:creator>mariuslucianand</dc:creator>
      <dc:date>2020-12-23T13:53:21Z</dc:date>
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