S32K358 ASIL Compliant Architecture Using MBDT

OllieSaunders — Fri, 27 Feb 2026 13:25:03 GMT

I am currently in development of a system using the S32K358 with MBDT in Simulink with the intent of supporting the ASIL capability of the chip.

I have been able to deploy my model on the S32K on a single core and in order to align with the ASIL capability of the chip I want to understand how to architecture the system and model to run on multiple cores.
The model has been architected such that it is split into 2 sections, the 'safety' layer which would be deployed on the ASIL D capable lockstep core, and the 'application' layer on the other core.

From reading some info on the community page there doesn't appear to be multicore support using MBDT for the S32K. Can you confirm if this is the case?

If not can you provide some insight into the best approach, for example would I have to develop the 'safety' layer using your S32DS whilst keeping the application code in Simulink?
I imagine this would need additional consideration for code generation, flashing and management of multiple files and MiL testing in the simulink environment.

As a follow up question, the application needs to be aware of the safety element and read various signals. What is the approach for intercore communication? Would there need to be a shared memory area that both cores can access and can this be managed using MBDT.

For reference I am currently using S32K3 1.4.0 and BMS 1.2.0 MBDT toolboxes.

Thanks for the support.

topic S32K358 ASIL Compliant Architecture Using MBDT in Model-Based Design Toolbox (MBDT)

S32K358 ASIL Compliant Architecture Using MBDT