LPCXpresso IDE中的主题 Re: Cycles per instruction?

Cycles per instruction?

lpcware — Thu, 16 Jun 2016 01:54:15 GMT

Content originally posted in LPCWare by Dave3891 on Wed Jul 13 16:45:24 MST 2011
Is there a list of assembly instructions and the amount of cycles each one takes for the M3 cortex (LPC1343)?

I am trying to figure out how long sections of assembly code takes.

Thanks
Dave

Re: Cycles per instruction?

lpcware — Thu, 16 Jun 2016 01:54:16 GMT

Content originally posted in LPCWare by Ex-Zero on Wed Jul 13 17:02:37 MST 2011
ARM Infocenter:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337i/index.html

Cortex ™-M3 Technical Reference Manual r2p0 - Chapter 18. Instruction Timing

PDF: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337g/DDI0337G_cortex_m3_r2p0_trm.pdf

Re: Cycles per instruction?

lpcware — Thu, 16 Jun 2016 01:54:17 GMT

Content originally posted in LPCWare by Dave3891 on Wed Jul 13 19:50:51 MST 2011
Thank you

Dave

Re: Cycles per instruction?

lpcware — Thu, 16 Jun 2016 01:54:17 GMT

Content originally posted in LPCWare by CodeRedSupport on Wed Jul 13 23:54:38 MST 2011
For future reference, we keep a list of useful ARM documentation in the following FAQ:

http://support.code-red-tech.com/CodeRedWiki/ArmCpuInfo

Regards,
CodeRedSupport

Re: Cycles per instruction?

lpcware — Thu, 16 Jun 2016 01:54:18 GMT

Content originally posted in LPCWare by micrio on Fri Jul 15 09:22:05 MST 2011
When calculating instruction timing you need to be aware of wait states imposed when accessing flash. You can get some odd behavior in tight loops depending the alignment of the code.

Pete.

Re: Cycles per instruction?

lpcware — Thu, 16 Jun 2016 01:54:19 GMT

Content originally posted in LPCWare by NXP_USA on Fri Jul 15 16:10:11 MST 2011
On the Cortex-M3: Most instructions are a single clock cycle except for branches, which are two clock cycles.

On the Cortex-M0: Most instructions are a single clock cycle unless they fetch data. When an instruction fetches data from memory (not immediate or register values), it takes two clock cycles (because the M0 core only has one bus). Branches are 3 clock cycles.

-NXP