LPCXpresso IDE中的主题 Re: How do you enable processor exception interrupts?

How do you enable processor exception interrupts?

lpcware — Thu, 16 Jun 2016 00:29:28 GMT

Content originally posted in LPCWare by amrbekhit on Tue Jan 04 09:10:49 MST 2011
Hello all,

As the question states, how do you enable exception interrupts? I'm trying to enable the bus fault, usage fault and memory management interrupts by using the following code:

NVIC_EnableIRQ(BusFault_IRQn);
NVIC_EnableIRQ(UsageFault_IRQn);
NVIC_EnableIRQ(MemoryManagement_IRQn);

but the processor raises a hard fault when trying to execute the first line, possibly because the IRQ numbers are negative. I'm using an LPC1752.

--Amr

Re: How do you enable processor exception interrupts?

lpcware — Thu, 16 Jun 2016 00:29:28 GMT

Content originally posted in LPCWare by TheFallGuy on Tue Jan 04 09:34:05 MST 2011
AFAIK, they are enabled be default - that is, if you cause one of those exceptions, you will end up in the exception handler for that fault without you having to specifically enable it.

Re: How do you enable processor exception interrupts?

lpcware — Thu, 16 Jun 2016 00:29:29 GMT

Content originally posted in LPCWare by Ex-Zero on Tue Jan 04 12:31:28 MST 2011

NVIC_EnableIRQ(BusFault_IRQn);
NVIC_EnableIRQ(UsageFault_IRQn);
NVIC_EnableIRQ(MemoryManagement_IRQn);

Your code is complete wrong

NVIC_EnableIRQ(...); uses ISER[0]-ISER[3] registers (0xE000E100 - 0xE000E11C)

USGFAULT, BUSFAULT and MEMFAULT must be enabled in SCB->SHCSR (0xE000ED24) with

SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk;
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk;
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;

defined in core_cm3.h (CMSISv1p30_LPC17xx\inc)

Reset values are 0.

You can control this bits in Peripherals View -> NVIC -> SYS_HANDLER_CSR

The following MM_FSR, BUS_FSR and USAGE_FSR can give you further information about the cause of the fault.

See -> UM10360 Chapter 4.3.10 System Handler Control and State Register