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    <title>topic Re: LPC-Link2 &amp; CAN in LPCXpresso IDE</title>
    <link>https://community.nxp.com/t5/LPCXpresso-IDE/LPC-Link2-CAN/m-p/536412#M5071</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by andersrosvall on Fri Nov 29 07:37:08 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;The schematic has been drawn by NXP long before it was decided to be an LPC4370 as main processor. Hence the generic pin names.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The LPC-Link2 is mainly a debug probe and focus is not on it being an evaluation board. Again, hence the generic pin names.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;You are correct that CAN-pins for one channel are available at J3 pin 11/12.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Kind Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Anders @ Embedded Artists &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 16 Jun 2016 00:23:40 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-16T00:23:40Z</dc:date>
    <item>
      <title>LPC-Link2 &amp; CAN</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/LPC-Link2-CAN/m-p/536411#M5070</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by LabRat on Wed Nov 27 06:56:45 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;We are just thinking about using LPC-Link2 as CAN-Device...&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;But we couldn't find CAN-pins in LPC-Link2 schematic??&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.embeddedartists.com%2Fsites%2Fdefault%2Ffiles%2Fsupport%2Fxpr%2Flink2%2FLPC-Link-II_Rev_C.pdf" rel="nofollow" target="_blank"&gt;http://www.embeddedartists.com/sites/default/files/support/xpr/link2/LPC-Link-II_Rev_C.pdf&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Even Serial Expansion Interface (J3) isn't offering CAN.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Perhaps it's a good idea to add a hint that GPIO5_8/9 (J3-11/12) is CAN0_RD/CAN0_TD&amp;nbsp; :) &lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Jun 2016 00:23:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/LPC-Link2-CAN/m-p/536411#M5070</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-16T00:23:39Z</dc:date>
    </item>
    <item>
      <title>Re: LPC-Link2 &amp; CAN</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/LPC-Link2-CAN/m-p/536412#M5071</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by andersrosvall on Fri Nov 29 07:37:08 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;The schematic has been drawn by NXP long before it was decided to be an LPC4370 as main processor. Hence the generic pin names.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The LPC-Link2 is mainly a debug probe and focus is not on it being an evaluation board. Again, hence the generic pin names.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;You are correct that CAN-pins for one channel are available at J3 pin 11/12.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Kind Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Anders @ Embedded Artists &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Jun 2016 00:23:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/LPC-Link2-CAN/m-p/536412#M5071</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-16T00:23:40Z</dc:date>
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