topic Re: New Ethernet Interface KSZ8051RNL in LPCXpresso IDE

New Ethernet Interface KSZ8051RNL

lpcware — Wed, 15 Jun 2016 23:11:23 GMT

Content originally posted in LPCWare by Luis Digital on Tue Sep 28 12:39:41 MST 2010
Hello,

The KSZ8051RNL is a new Ethernet interface, is very inexpensive and includes the 4 resistors of 49.9 ohms. The only problem is that is bigger and take more PCB.

It would be great NXP chips include this interface, would be a great saving money, space, and would end the problems of compatibility.

What do you think?

Re: New Ethernet Interface KSZ8051RNL

lpcware — Wed, 15 Jun 2016 23:11:24 GMT

Content originally posted in LPCWare by UlfZiemann on Wed Oct 20 05:25:10 MST 2010
The KSZ8051RNL supports RMII: http://www.micrel.com/_PDF/Ethernet/ksz8051_pb.pdf as an interface to the microcontroller.

The LPC1758 from NXP supports RMII, too.

Where do you see a problem?

Ulf

Re: New Ethernet Interface KSZ8051RNL

lpcware — Wed, 15 Jun 2016 23:11:25 GMT

Content originally posted in LPCWare by Luis Digital on Wed Oct 20 06:10:41 MST 2010

Quote: UlfZiemann
The KSZ8051RNL supports RMII: http://www.micrel.com/_PDF/Ethernet/ksz8051_pb.pdf as an interface to the microcontroller.

The LPC1758 from NXP supports RMII, too.

Where do you see a problem?

Ulf

I said:
The only problem is that is bigger and take more PCB.

This chip also has more pins, and control signals that need resistance. So in the end saving money is not. Significant savings could be ARM chips with Ethernet, as is standard for other manufacturers such as Microchip.

Re: New Ethernet Interface KSZ8051RNL

lpcware — Wed, 15 Jun 2016 23:11:26 GMT

Content originally posted in LPCWare by ashgupta28 on Tue Dec 09 01:50:46 MST 2014
I am also using custom board with LPC18xx with KSZ8863RLL. I am trying to read & write PHY registers. Actually I am using CLOCK MODE & MDIO SMII Mode (RMII mode) to access registers. I guess as per the MII format, only 5bit register address & 5 bit Phy address can be used.
I am using 25MHZ crystal populated at X1 & X2 at PHY switch.

BUT I AM GETTING GARBAGE VALUES WHILE READING THESE KSZ8863RLL REGISTERS

HERE ARE THE STEPS I AM FOLLOWING:-
1.Configure the LPC processor clock & enabled the RMII interface of LPC
2.Configure the PHY address PHY 1( this configuration helps to create the RMII frame format and adding the PHY address 0x01 in PHY address Bits[4:0]
3.As per our set up, LPC processor is receiving 50MHz reference clock.(Please correct me if I am wrong). So what settings need to be in done in LPC as per clock. I have selected CLK_M3_ETHERNET/102

4.After that I tried to read MII_PHYSID1(0x02) & MII_PHYSID2(0x03) with PHY address 0x01. It will return only 16bit data (should return 0x0022 & 0x1430) as per the format. But I receive only the garbage value. Also I tried to connect the LAN cable at port 1 & tried to read the MII_BMSR to check the LINK up or down but the value I am reading is 0x0000 every time. The LEDs & LINK LEDs blinks properly after connecting the cable but still I am getting 0x00 value.

if (lpc_mii_read(0x00, &tmp) != SUCCESS) {
return ERROR;
}

I have selected PHY address 1 & trying to read 0x00 register
lpc_read_read is actually configuring the packet as per the datasheet & sending to Micrel chip