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    <title>topic Re: UART usage when &amp;quot;RX Trigger Level!=0&amp;quot; in LPCXpresso IDE</title>
    <link>https://community.nxp.com/t5/LPCXpresso-IDE/UART-usage-when-quot-RX-Trigger-Level-0-quot/m-p/534515#M4136</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by MikeSimmonds on Wed Nov 07 02:12:44 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;[FONT=Tahoma][SIZE=1]The manual does not state explicitly to read the received character register multiple times, but[/SIZE][/FONT][FONT=Tahoma][SIZE=1] it does say:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;[/SIZE][/FONT]&lt;/SPAN&gt;&lt;HR /&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;Quote: &lt;/STRONG&gt;&lt;BR /&gt;[FONT=Tahoma][SIZE=1]The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains &lt;BR /&gt;the oldest character received and can be read via the bus interface. The LSB (bit 0) &lt;BR /&gt;represents the “oldest” received data bit. If the character received is less than 8 bits, the &lt;BR /&gt;unused MSBs are padded with zeroes.[/SIZE][/FONT]&lt;/SPAN&gt;&lt;HR /&gt;&lt;SPAN&gt;[FONT=Tahoma][SIZE=1]&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I know that the manual is frustrating and ambiguous at times:(, but it is all&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;we have and, usually, the information is there (or can be inferred) somewhere.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Cheers, Mike&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;[/SIZE][/FONT]&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 23:12:13 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T23:12:13Z</dc:date>
    <item>
      <title>UART usage when "RX Trigger Level!=0"</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/UART-usage-when-quot-RX-Trigger-Level-0-quot/m-p/534512#M4133</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by BM10 on Tue Nov 06 13:16:23 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi all.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I've been trying to find an answer to a question that has been bugging me for quite some time. I am sure that the answer is simple but I am also a newbie, so be patient.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;This is the scenario:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am using a LPC1769 UART port to communicate with a GPS module. So far, I was able to transmit data to the GPS module successfully.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;However, on the receiving part, I was not so lucky.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;My objective is to build the receiving code that triggers as little UART interruptions as possible.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;From what I've seen so far on the User Manual, I can accomplishe this by:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;1- Operating the UART port using DMA&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;or&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2- Configuring the "RX Trigger Level" on FCR register to 14 characters&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Once this is done I'll be able to do some test and check which option has better performance.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;My real problem concerns option "2". How to use the UART with "RX Trigger Level" different from 1 character?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;From what I understood, the "RX Trigger Level" "determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated." (UM §14.4.6)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Question1: Considering that the received data is stores in Receiver Buffer Register (wich is only 1 byte long), where are the remaining characters stored when "RX Trigger Level!=0" and the UART interrupt is triggered?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Question2: "§14.2 Features" state that LPC1769 has "16 byte Receive and Transmit FIFOs". Where are they? Which register? How can I use them&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I hope I was able to explain my doubts clearly.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Any clarification, tutorial and/or sample code is wellcome (All the sample code I found so far is using "RX Trigger Level==0").&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks in advance.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 23:12:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/UART-usage-when-quot-RX-Trigger-Level-0-quot/m-p/534512#M4133</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T23:12:11Z</dc:date>
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    <item>
      <title>Re: UART usage when "RX Trigger Level!=0"</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/UART-usage-when-quot-RX-Trigger-Level-0-quot/m-p/534513#M4134</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by MikeSimmonds on Tue Nov 06 14:01:07 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;[FONT=Tahoma][SIZE=1]The fifo registers are not visible to the user.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;After setting the trigger level (e.g. to 14), you will get an interrupt after the 14th character has been&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;received. [Assuming that you enabled the RBRIE bit in the IER register.]&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In the interrupt, read the IIR to see what interrupt occured.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;If INTID is 2, you can read (and save) the RBR register 14 (or whatever) times, each time it will&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;return the next character from the (hardware) fifo.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;You can also get a CTI interrupts if there is a least 1 character in the fifo (but less than the trigger&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;level) and 3 to 3.5 character times have passed without reading the fifo.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;See the text description after the IIR register in the user manual.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Cheers, Mike&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;[/SIZE][/FONT]&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 23:12:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/UART-usage-when-quot-RX-Trigger-Level-0-quot/m-p/534513#M4134</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T23:12:12Z</dc:date>
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    <item>
      <title>Re: UART usage when "RX Trigger Level!=0"</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/UART-usage-when-quot-RX-Trigger-Level-0-quot/m-p/534514#M4135</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by BM10 on Tue Nov 06 17:20:34 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;This sentence:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;"... you can read (and save) the RBR register 14 (or whatever) times, each time it will return the next character from the (hardware) fifo."&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;clarified any doubt I had.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Perhaps I didn't read the UM with the necessary attention or my English betrayed me (and something got lost in translation), but I don't recall reading that RBR should be read "trigger level" times.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Either way, the doubt I had, vanished.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you very much for the support Mike.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Cordially.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 23:12:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/UART-usage-when-quot-RX-Trigger-Level-0-quot/m-p/534514#M4135</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T23:12:12Z</dc:date>
    </item>
    <item>
      <title>Re: UART usage when "RX Trigger Level!=0"</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/UART-usage-when-quot-RX-Trigger-Level-0-quot/m-p/534515#M4136</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by MikeSimmonds on Wed Nov 07 02:12:44 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;[FONT=Tahoma][SIZE=1]The manual does not state explicitly to read the received character register multiple times, but[/SIZE][/FONT][FONT=Tahoma][SIZE=1] it does say:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;[/SIZE][/FONT]&lt;/SPAN&gt;&lt;HR /&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;Quote: &lt;/STRONG&gt;&lt;BR /&gt;[FONT=Tahoma][SIZE=1]The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains &lt;BR /&gt;the oldest character received and can be read via the bus interface. The LSB (bit 0) &lt;BR /&gt;represents the “oldest” received data bit. If the character received is less than 8 bits, the &lt;BR /&gt;unused MSBs are padded with zeroes.[/SIZE][/FONT]&lt;/SPAN&gt;&lt;HR /&gt;&lt;SPAN&gt;[FONT=Tahoma][SIZE=1]&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I know that the manual is frustrating and ambiguous at times:(, but it is all&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;we have and, usually, the information is there (or can be inferred) somewhere.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Cheers, Mike&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;[/SIZE][/FONT]&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 23:12:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/UART-usage-when-quot-RX-Trigger-Level-0-quot/m-p/534515#M4136</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T23:12:13Z</dc:date>
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