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    <title>topic LPC1226 SSP FIFO problem in LPCXpresso IDE</title>
    <link>https://community.nxp.com/t5/LPCXpresso-IDE/LPC1226-SSP-FIFO-problem/m-p/534112#M3935</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by samc on Fri Feb 10 06:41:45 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hello, &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;just wanted to post this, might save some time:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I found the SSP interface on LPC1226 acts strange:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I set SSP_CLK to 36MHZ and also CPU clock was 36MHZ, everything working fine.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Then switched cpu clock to 12MHz by SYSAHBCLKDIV and thats where the problem started: the SSP FIFO didnt act as a FIFO anymore, more like an eight byte shift register. Resetting the pheriperal didnt help also.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Solution:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Finally, I set the SSP_CLK to 12MHz and everything went fine.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Samc&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 16 Jun 2016 02:59:28 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-16T02:59:28Z</dc:date>
    <item>
      <title>LPC1226 SSP FIFO problem</title>
      <link>https://community.nxp.com/t5/LPCXpresso-IDE/LPC1226-SSP-FIFO-problem/m-p/534112#M3935</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by samc on Fri Feb 10 06:41:45 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hello, &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;just wanted to post this, might save some time:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I found the SSP interface on LPC1226 acts strange:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I set SSP_CLK to 36MHZ and also CPU clock was 36MHZ, everything working fine.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Then switched cpu clock to 12MHz by SYSAHBCLKDIV and thats where the problem started: the SSP FIFO didnt act as a FIFO anymore, more like an eight byte shift register. Resetting the pheriperal didnt help also.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Solution:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Finally, I set the SSP_CLK to 12MHz and everything went fine.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Samc&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 16 Jun 2016 02:59:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPCXpresso-IDE/LPC1226-SSP-FIFO-problem/m-p/534112#M3935</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-16T02:59:28Z</dc:date>
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